From patchwork Thu Sep 20 09:58:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 1483541 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id BF01B3FD40 for ; Thu, 20 Sep 2012 09:59:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752375Ab2ITJ7P (ORCPT ); Thu, 20 Sep 2012 05:59:15 -0400 Received: from mail-qc0-f174.google.com ([209.85.216.174]:34927 "EHLO mail-qc0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751062Ab2ITJ7O (ORCPT ); Thu, 20 Sep 2012 05:59:14 -0400 Received: by qcro28 with SMTP id o28so1558546qcr.19 for ; Thu, 20 Sep 2012 02:59:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=RGrCPEemo1p141Nsz/93KiL5iCOzM+hKFQO8gSK2AEg=; b=rpNFtksOnZgDyfzzIL5UztJCl7i/Z5u2O2EzJIXIT0oeJBcJb5uFZu3Dnqfftw3nI+ FPijISbyRjQnmNJ0kfHl0agVGXEakZwhBgH4/QJZpQXS+txEdlxxiBMsIoz7E6AEvAhT bvYr1Zj1hB3vTR8XWejeGz6w1J1a3EXX0PQ3Kh/b1FEmytQ/2UpUBwpDDAD1sgzGXWQy NZUTr6125lGx0Zx7GNoQWLNjgfDQeEut/YUhPrAYTSOw1aZr+Iqak6bYRtPEs4pY3ooh QatzOpchMoq0Oz0X4chfXw/fGBYotJthPyUngO+yERq3s1zhZK1aW1qR8njDk9TQqmTx V+yQ== Received: by 10.224.193.69 with SMTP id dt5mr3230641qab.2.1348135154202; Thu, 20 Sep 2012 02:59:14 -0700 (PDT) MIME-Version: 1.0 Received: by 10.49.103.135 with HTTP; Thu, 20 Sep 2012 02:58:53 -0700 (PDT) In-Reply-To: <1347434097-7924-2-git-send-email-horms@verge.net.au> References: <1347434097-7924-1-git-send-email-horms@verge.net.au> <1347434097-7924-2-git-send-email-horms@verge.net.au> From: Catalin Marinas Date: Thu, 20 Sep 2012 10:58:53 +0100 X-Google-Sender-Auth: B4mkRcv1h48CAJ9H1bs_yPCp254 Message-ID: Subject: Re: [PATCH 1/2] arm: Add ARM ERRATA 775420 workaround To: Simon Horman Cc: Russell King , Paul Mundt , Magnus Damm , linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org On 12 September 2012 08:14, Simon Horman wrote: > +config ARM_ERRATA_775420 > + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" > + depends on CPU_V7 > + help > + This option enables the workaround for the 775420 Cortex-A9 (r2p2, > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance > + operation aborts with MMU exception, it might cause the processor > + deadlock. This workaround puts DSB before executing ISB at the > + beginning of the abort exception handler. > + > endmenu The only case where we can get an abort on cache maintenance is v7_coherent_user_range(). I don't think we have any ISB on the exception handling path for this function, so we could just add the DSB there: --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range) * isn't mapped, fail with -EFAULT. */ 9001: +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif mov r0, #-EFAULT mov pc, lr UNWIND(.fnend )