From patchwork Fri May 7 10:05:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 97712 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o47A5Ow2020387 for ; Fri, 7 May 2010 10:05:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756132Ab0EGKFX (ORCPT ); Fri, 7 May 2010 06:05:23 -0400 Received: from mail.gmx.net ([213.165.64.20]:48430 "HELO mail.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1755911Ab0EGKFW (ORCPT ); Fri, 7 May 2010 06:05:22 -0400 Received: (qmail invoked by alias); 07 May 2010 10:05:20 -0000 Received: from p57BD1BFA.dip0.t-ipconnect.de (EHLO axis700.grange) [87.189.27.250] by mail.gmx.net (mp067) with SMTP; 07 May 2010 12:05:20 +0200 X-Authenticated: #20450766 X-Provags-ID: V01U2FsdGVkX19WejE1Py9W6mF3kKXpsOW9nLxIBgQ+VTpvQXEFh4 2mgmp/IbVI8I/M Received: from lyakh (helo=localhost) by axis700.grange with local-esmtp (Exim 4.63) (envelope-from ) id 1OAKQw-0001jG-0z; Fri, 07 May 2010 12:05:26 +0200 Date: Fri, 7 May 2010 12:05:25 +0200 (CEST) From: Guennadi Liakhovetski To: "linux-sh@vger.kernel.org" cc: Magnus Damm , linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, Tomi Valkeinen Subject: [PATCH 2.5/4] ARM: add LCDC and MIPI DSI-Tx clock definitions to sh7372 In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Y-GMX-Trusted: 0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 07 May 2010 10:06:15 +0000 (UTC) diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index abbc380..66ee47a 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -264,8 +264,12 @@ struct clk div6_clks[] = { #define R_CLK (&r_clk) #define HP_CLK (&div4_clks[DIV4_HP]) +#define B_CLK (&div4_clks[DIV4_B]) static struct clk mstp_clks[] = { + MSTP("lcdc0", B_CLK, SMSTPCR1, 0, 0), + MSTP("lcdc1", B_CLK, SMSTPCR1, 17, 0), + MSTP("dsitx", B_CLK, SMSTPCR1, 18, 0), MSTP("sdhi0", HP_CLK, SMSTPCR3, 14, 0), MSTP("sdhi1", HP_CLK, SMSTPCR3, 13, 0), MSTP("keysc0", R_CLK, SMSTPCR4, 3, 0),