From patchwork Mon Jul 26 16:20:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 114301 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6QGKUZt020177 for ; Mon, 26 Jul 2010 16:20:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754013Ab0GZQUc (ORCPT ); Mon, 26 Jul 2010 12:20:32 -0400 Received: from mailout-de.gmx.net ([213.165.64.23]:58115 "HELO mail.gmx.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with SMTP id S1753477Ab0GZQUc (ORCPT ); Mon, 26 Jul 2010 12:20:32 -0400 Received: (qmail invoked by alias); 26 Jul 2010 16:20:30 -0000 Received: from p57BD0776.dip0.t-ipconnect.de (EHLO axis700.grange) [87.189.7.118] by mail.gmx.net (mp001) with SMTP; 26 Jul 2010 18:20:30 +0200 X-Authenticated: #20450766 X-Provags-ID: V01U2FsdGVkX18O1f1chfoOcVZ+IkjNRiE0X2qkCgoR1mAd8t2k6a EMAPTl0c8M2TGz Received: from lyakh (helo=localhost) by axis700.grange with local-esmtp (Exim 4.63) (envelope-from ) id 1OdQQ5-0002XX-Ps; Mon, 26 Jul 2010 18:20:49 +0200 Date: Mon, 26 Jul 2010 18:20:49 +0200 (CEST) From: Guennadi Liakhovetski To: Linux Media Mailing List cc: "linux-sh@vger.kernel.org" Subject: [PATCH 1/5] V4L2: mediabus: add 12-bit Bayer and YUV420 pixel formats In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Y-GMX-Trusted: 0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 26 Jul 2010 16:20:33 +0000 (UTC) diff --git a/include/media/v4l2-mediabus.h b/include/media/v4l2-mediabus.h index 865cda7..584e1b1 100644 --- a/include/media/v4l2-mediabus.h +++ b/include/media/v4l2-mediabus.h @@ -41,6 +41,11 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_MBUS_FMT_SGRBG8_1X8, + V4L2_MBUS_FMT_SBGGR12_1X12, + V4L2_MBUS_FMT_YUYV8_1_5X8, + V4L2_MBUS_FMT_YVYU8_1_5X8, + V4L2_MBUS_FMT_UYVY8_1_5X8, + V4L2_MBUS_FMT_VYUY8_1_5X8, }; /**