From patchwork Tue Sep 18 23:10:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 1475011 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 5020B3FCFC for ; Tue, 18 Sep 2012 23:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754713Ab2IRXKg (ORCPT ); Tue, 18 Sep 2012 19:10:36 -0400 Received: from moutng.kundenserver.de ([212.227.126.171]:54105 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752149Ab2IRXKf (ORCPT ); Tue, 18 Sep 2012 19:10:35 -0400 Received: from axis700.grange (dslb-094-221-112-134.pools.arcor-ip.net [94.221.112.134]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MAidD-1TLUNu2c2d-00Bmib; Wed, 19 Sep 2012 01:10:26 +0200 Received: by axis700.grange (Postfix, from userid 1000) id 1097C189B0D; Wed, 19 Sep 2012 01:10:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id EDC46189AF7; Wed, 19 Sep 2012 01:10:24 +0200 (CEST) Date: Wed, 19 Sep 2012 01:10:24 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: linux-mmc@vger.kernel.org cc: Tetsuyuki Kobayashi , yusuke.goda.sx@renesas.com, Kuninori Morimoto , Paul Mundt , Magnus Damm , linux-sh@vger.kernel.org, Kuninori Morimoto Subject: [PATCH] mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ Message-ID: MIME-Version: 1.0 X-Provags-ID: V02:K0:liDkzD09DE5xujv9U6QDWukJQylWDTqkvTPFQJL1lRj P46ewkNooDGMAYh+d5SivQMksGiWKDsfxiy7KED6LP+cMztgHj UhJcgivQz9NF+X3TjLu6CqiO7T56VOrylapkUwCy/clY9cC/b8 Z+qcLSRMuOXtdOny59lHshudfpjGWvQm3D/GXWNGdZF4Q2+DyE a7jKgeRva8oiHDi7of3Z5D8B/fzA8cOhXPa7cY+/FdJDS8meVk gt1BDEA3r049lLv8K8QhRkfLT2FRHbqHap4hXeun/I49Gj4PTt 6FtWjRDAOZEFGhJryKoSsP+3ZukeVxVlrDaGFPQyNXYvOSEhgd HRRpUFANbtLAQr34FuXEUZZEzGwz28BbnHCXFRN8hpFehF/uYc NI81FOlQurfwg== Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Upon completion of a MMC_WRITE_MULTIPLE_BLOCK command MMCIF issues an IRQ with the DTRANE bit set and often with one or several of CMD12 bits set. If those interrupts are not acknowledged, an additional interrupt can be produced and will be delivered later, possibly, when the transaction has already been completed. To prevent this from happening, CMD12 completion interrupt sources have to be cleared too upon reception of an DTRANE IRQ. Signed-off-by: Guennadi Liakhovetski Tested-by: Tetsuyuki Kobayashi --- Tested on kzm9g and mackerel. Kobayashi-san, this fixes spurious interrupts, that you are observing. drivers/mmc/host/sh_mmcif.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 82bf921..387bf63 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -1213,7 +1213,9 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); } else if (state & INT_DTRANE) { - sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); + sh_mmcif_writel(host->addr, MMCIF_CE_INT, + ~(INT_CMD12DRE | INT_CMD12RBE | + INT_CMD12CRE | INT_DTRANE)); sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); } else if (state & INT_CMD12RBE) { sh_mmcif_writel(host->addr, MMCIF_CE_INT,