From patchwork Thu Jun 13 08:58:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2715011 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 687799F3B5 for ; Thu, 13 Jun 2013 08:58:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 30B38201CC for ; Thu, 13 Jun 2013 08:58:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1940B201C8 for ; Thu, 13 Jun 2013 08:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757527Ab3FMI6q (ORCPT ); Thu, 13 Jun 2013 04:58:46 -0400 Received: from moutng.kundenserver.de ([212.227.17.10]:51651 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756298Ab3FMI6p (ORCPT ); Thu, 13 Jun 2013 04:58:45 -0400 Received: from axis700.grange (dslb-088-077-162-009.pools.arcor-ip.net [88.77.162.9]) by mrelayeu.kundenserver.de (node=mreu1) with ESMTP (Nemesis) id 0MW7C9-1Up5Z504ID-00X6qy; Thu, 13 Jun 2013 10:58:42 +0200 Received: by axis700.grange (Postfix, from userid 1000) id 815D940BB5; Thu, 13 Jun 2013 10:58:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 7655040BB4; Thu, 13 Jun 2013 10:58:41 +0200 (CEST) Date: Thu, 13 Jun 2013 10:58:41 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: linux-sh@vger.kernel.org cc: Laurent Pinchart , linux-sh@vger.kernel.org, Magnus Damm , Simon Horman Subject: [PATCH v2 1/2] ARM: shmobile: wait for MSTP clock status to toggle, when enabling it Message-ID: MIME-Version: 1.0 X-Provags-ID: V02:K0:SK4pJuublbp3yAA8hV//WZfwFIdLX6BeDHhApFXE6QU I8ygKZJ2fpvkqA+qTXjJ2KQDHFyejr0Pc+P6Fs49xRFmGH+7j4 b8ckkaRg1U4Yzl44CFFzXvqkniW1u+HO7Du2OgVYm5RBGDRX8k 5DnyOjQNugk8lhd7Tlf5S0HvL+OIySI8DHiwIaBeywX9gmXOaD uw5kT9bTd/CJp8isjnmccEQTr1OLsPoBFuMT06SHFn8MO4KFje ruOxYiIB8y9ASmNJNfyykki8+b7l4ykZGrmMU5xeRFi3XeLIjW AzTFpQO5lcFHY8mnrSacPpuiq1VY4/s6AOqqOHw9ARnTzSsw+3 skiyRwlxUfHLVUUGRaLilYlrUOO3fz/L1hI/Rauw/BIMZ/7OeQ 1bY9I5kBtwgGQ== Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically enable and disable peripheral clocks. To make sure the clock has really started we have to read back its status register until it confirms success. Signed-off-by: Guennadi Liakhovetski --- v2: 1. removed "const" reom read accessors to fix compiler warnings 2. added a "(void __iomem *)" cast, as suggested by Laurent drivers/sh/clk/cpg.c | 38 ++++++++++++++++++++++++++++++++++++++ include/linux/sh_clk.h | 29 +++++++++++++++++------------ 2 files changed, 55 insertions(+), 12 deletions(-) diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 1ebe67c..87de622 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk) iowrite32(value, clk->mapped_reg); } +static unsigned int r8(void __iomem *addr) +{ + return ioread8(addr); +} + +static unsigned int r16(void __iomem *addr) +{ + return ioread16(addr); +} + +static unsigned int r32(void __iomem *addr) +{ + return ioread32(addr); +} + static int sh_clk_mstp_enable(struct clk *clk) { sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); + if (clk->status_reg) { + unsigned int (*read)(void __iomem *addr); + int i; + void __iomem *mapped_status = (phys_addr_t)clk->status_reg - + (phys_addr_t)clk->enable_reg + clk->mapped_reg; + + if (clk->flags & CLK_ENABLE_REG_8BIT) + read = r8; + else if (clk->flags & CLK_ENABLE_REG_16BIT) + read = r16; + else + read = r32; + + for (i = 1000; + (read(mapped_status) & (1 << clk->enable_bit)) && i; + i--) + cpu_relax(); + if (!i) { + pr_err("cpg: failed to enable %p[%d]\n", + clk->enable_reg, clk->enable_bit); + return -ETIMEDOUT; + } + } return 0; } diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index 60c7239..affc8d8 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h @@ -52,6 +52,7 @@ struct clk { unsigned long flags; void __iomem *enable_reg; + void __iomem *status_reg; unsigned int enable_bit; void __iomem *mapped_reg; @@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target, unsigned long *best_freq, unsigned long *parent_freq, unsigned int div_min, unsigned int div_max); -#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ -{ \ - .parent = _parent, \ - .enable_reg = (void __iomem *)_enable_reg, \ - .enable_bit = _enable_bit, \ - .flags = _flags, \ +#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ +{ \ + .parent = _parent, \ + .enable_reg = (void __iomem *)_enable_reg, \ + .enable_bit = _enable_bit, \ + .status_reg = (void __iomem *)_status_reg, \ + .flags = _flags, \ } -#define SH_CLK_MSTP32(_p, _r, _b, _f) \ - SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) +#define SH_CLK_MSTP32(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT) -#define SH_CLK_MSTP16(_p, _r, _b, _f) \ - SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) +#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \ + SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT) -#define SH_CLK_MSTP8(_p, _r, _b, _f) \ - SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) +#define SH_CLK_MSTP16(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT) + +#define SH_CLK_MSTP8(_p, _r, _b, _f) \ + SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT) int sh_clk_mstp_register(struct clk *clks, int nr);