From patchwork Tue Jul 2 15:46:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2813631 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1B490BF4A1 for ; Tue, 2 Jul 2013 15:46:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6268720198 for ; Tue, 2 Jul 2013 15:46:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A92A20185 for ; Tue, 2 Jul 2013 15:46:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753896Ab3GBPqK (ORCPT ); Tue, 2 Jul 2013 11:46:10 -0400 Received: from moutng.kundenserver.de ([212.227.126.186]:51401 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753890Ab3GBPqJ (ORCPT ); Tue, 2 Jul 2013 11:46:09 -0400 Received: from axis700.grange (dslb-178-009-253-215.pools.arcor-ip.net [178.9.253.215]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MNQCL-1Us6pb45LF-007W4N; Tue, 02 Jul 2013 17:46:07 +0200 Received: by axis700.grange (Postfix, from userid 1000) id 8C81640BB4; Tue, 2 Jul 2013 17:46:06 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 8998540BB3; Tue, 2 Jul 2013 17:46:06 +0200 (CEST) Date: Tue, 2 Jul 2013 17:46:06 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: linux-sh@vger.kernel.org cc: "Koul, Vinod" , Magnus Damm , linux-kernel@vger.kernel.org, Kuninori Morimoto Subject: [PATCH 3/3] DMA: shdma: support the new CHCLR register layout In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Provags-ID: V02:K0:ajDgb5x6JW2Gd/ZL1HYHChvjFRetAcyi2S1OTqbq0t8 hBi/BVN9TWwjZImiss6LiuXfRAuiuNgNn4PnjvAsE24nRPWpcZ ylwXwq0YTx7s8O1ceg2zrYL814ANWX9y6/8j2/zN2HjSQoqeUb zjtVJwiosc5GLilLMT8TatV/bFPrTQKalKvlG7epH34Av8zkhV GqWJAZUNE3gXkhFHjAyUGpDuUGavSIlTIrvqM+Xh/EovbS/vM2 nBeHQpPT40AgWQIeIjzoG8QwXcnBH0N+9R1sbpm/SKLLIL2U1+ MEd8dary7zTclMLzfgkrYucdnpiZEuVxPFp44Ab9h9jdxDfjxW 0zKXkju+NAg6irP4zqNHDcyk8qaKU2K8MImgfrRO1zvDtSbMp7 174aa/SGnieCQ== Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On newer r-car SoCs the CHCLR register only contains one bit per channel, to which a 1 has to be written to reset the channel. Older SoC versions had one CHCLR register per channel, to which a 0 must be written to reset the channel and clear its buffers. This patch adds support for the newer layout. Signed-off-by: Guennadi Liakhovetski --- drivers/dma/sh/shdma.c | 6 ++++-- include/linux/sh_dma.h | 12 +++++++++++- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/shdma.c b/drivers/dma/sh/shdma.c index 64eb7fb..883a4de 100644 --- a/drivers/dma/sh/shdma.c +++ b/drivers/dma/sh/shdma.c @@ -54,9 +54,11 @@ static LIST_HEAD(sh_dmae_devices); static void channel_clear(struct sh_dmae_chan *sh_dc) { struct sh_dmae_device *shdev = to_sh_dev(sh_dc); + const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel + + sh_dc->shdma_chan.id; + u32 val = chan_pdata->chclr_bit < 0 ? 0 : 1 << chan_pdata->chclr_bit; - __raw_writel(0, shdev->chan_reg + - shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset); + __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset); } static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h index 4e83f3e..9316a1d 100644 --- a/include/linux/sh_dma.h +++ b/include/linux/sh_dma.h @@ -33,11 +33,21 @@ struct sh_dmae_slave_config { char mid_rid; }; +/** + * struct sh_dmae_channel - DMAC channel platform data + * @offset: register offset within the main IOMEM resource + * @dmars: channel DMARS register offset + * @chclr_offset: channel CHCLR register offset + * @dmars_bit: channel DMARS field offset within the register + * @chclr_bit: > 0: bit position, to be set to reset the channel + * < 0: CHCLR has to be cleared to clear channel's buffers + */ struct sh_dmae_channel { unsigned int offset; unsigned int dmars; - unsigned int dmars_bit; unsigned int chclr_offset; + unsigned char dmars_bit; + signed char chclr_bit; }; struct sh_dmae_pdata {