diff mbox

[05/10] arm64: dts: r8a7795: Add pmu device nodes

Message ID a6b6b478459be0c5614626ba6ac95df05a7fc5e9.1450401186.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit a6b6b478459be0c5614626ba6ac95df05a7fc5e9
Headers show

Commit Message

Simon Horman Dec. 18, 2015, 2:29 a.m. UTC
From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>

Enabling the performance monitor unit on r8a7795.

Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Sudeep Holla Dec. 18, 2015, 10:16 a.m. UTC | #1
On 18/12/15 02:29, Simon Horman wrote:
> From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>
> Enabling the performance monitor unit on r8a7795.
>
> Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index 4d43cf31418f..b9229a49dabc 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -230,6 +230,18 @@
>   			power-domains = <&cpg>;
>   		};
>
> +		pmu {
> +			compatible = "arm,armv8-pmuv3";

Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned this
for some shmobile platform recently.
Dirk Behme Dec. 18, 2015, 10:44 a.m. UTC | #2
On 18.12.2015 11:16, Sudeep Holla wrote:
>
>
> On 18/12/15 02:29, Simon Horman wrote:
>> From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>
>> Enabling the performance monitor unit on r8a7795.
>>
>> Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
>> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>> ---
>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> index 4d43cf31418f..b9229a49dabc 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>> @@ -230,6 +230,18 @@
>>               power-domains = <&cpg>;
>>           };
>>
>> +        pmu {
>> +            compatible = "arm,armv8-pmuv3";
>
> Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned this
> for some shmobile platform recently.


Yes. But as this patch has been applied already to some branches, I 
incorporated your a57-pmu hint with an additional update patch:

http://marc.info/?l=linux-sh&m=145011467914857

Feel free to squash if still possible.

Best regards

Dirk

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Sudeep Holla Dec. 18, 2015, 10:47 a.m. UTC | #3
On 18/12/15 10:44, Dirk Behme wrote:
> On 18.12.2015 11:16, Sudeep Holla wrote:
>>
>>
>> On 18/12/15 02:29, Simon Horman wrote:
>>> From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>>
>>> Enabling the performance monitor unit on r8a7795.
>>>
>>> Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
>>> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>> ---
>>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
>>>   1 file changed, 12 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> index 4d43cf31418f..b9229a49dabc 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>> @@ -230,6 +230,18 @@
>>>               power-domains = <&cpg>;
>>>           };
>>>
>>> +        pmu {
>>> +            compatible = "arm,armv8-pmuv3";
>>
>> Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned this
>> for some shmobile platform recently.
>
>
> Yes. But as this patch has been applied already to some branches, I
> incorporated your a57-pmu hint with an additional update patch:
>
> http://marc.info/?l=linux-sh&m=145011467914857
>
> Feel free to squash if still possible.
>

Ah OK, I didn't know the exact dts name, sorry for the noise.
Better if it was posted as part of this series :)
Dirk Behme Jan. 9, 2016, 6:36 a.m. UTC | #4
On 18.12.2015 11:47, Sudeep Holla wrote:
>
>
> On 18/12/15 10:44, Dirk Behme wrote:
>> On 18.12.2015 11:16, Sudeep Holla wrote:
>>>
>>>
>>> On 18/12/15 02:29, Simon Horman wrote:
>>>> From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>>>
>>>> Enabling the performance monitor unit on r8a7795.
>>>>
>>>> Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
>>>> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>>> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>>>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>>> ---
>>>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
>>>>   1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> index 4d43cf31418f..b9229a49dabc 100644
>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>> @@ -230,6 +230,18 @@
>>>>               power-domains = <&cpg>;
>>>>           };
>>>>
>>>> +        pmu {
>>>> +            compatible = "arm,armv8-pmuv3";
>>>
>>> Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned
>>> this
>>> for some shmobile platform recently.
>>
>>
>> Yes. But as this patch has been applied already to some branches, I
>> incorporated your a57-pmu hint with an additional update patch:
>>
>> http://marc.info/?l=linux-sh&m=145011467914857
>>
>> Feel free to squash if still possible.
>>
>
> Ah OK, I didn't know the exact dts name, sorry for the noise.
> Better if it was posted as part of this series :)


I finally found some time to test this

http://marc.info/?l=linux-sh&m=145011467914857

and surprisingly it doesn't seem to work:

Using "arm,cortex-a57-pmu" results in

hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7 counters 
available
hw perfevents: failed to probe PMU!
hw perfevents: failed to register PMU devices!

while switching back to "arm,armv8-pmuv3" successfully gives

hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available

without any further error messages.

Any idea?

Best regards

Dirk



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Sudeep Holla Jan. 11, 2016, 10:18 a.m. UTC | #5
On 09/01/16 06:36, Dirk Behme wrote:
> On 18.12.2015 11:47, Sudeep Holla wrote:
>>
>>
>> On 18/12/15 10:44, Dirk Behme wrote:
>>> On 18.12.2015 11:16, Sudeep Holla wrote:

[...]

>>>>
>>>> Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned
>>>> this for some shmobile platform recently.
>>>
>>> Yes. But as this patch has been applied already to some branches, I
>>> incorporated your a57-pmu hint with an additional update patch:
>>>
>>> http://marc.info/?l=linux-sh&m=145011467914857
>>>
>>> Feel free to squash if still possible.
>>>
>>
>> Ah OK, I didn't know the exact dts name, sorry for the noise.
>> Better if it was posted as part of this series :)
>
>
> I finally found some time to test this
>
> http://marc.info/?l=linux-sh&m=145011467914857
>
> and surprisingly it doesn't seem to work:
>
> Using "arm,cortex-a57-pmu" results in
>
> hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7 counters available

I had a quick look at the DT in the link above and IIUC A57 PMU's are
successfully probed.

> hw perfevents: failed to probe PMU!
> hw perfevents: failed to register PMU devices!
>

This must be for A53 PMUs. So I suspect if the update DT is passed
correctly to the kernel.

> while switching back to "arm,armv8-pmuv3" successfully gives
>
> hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
>
> without any further error messages.
>
> Any idea?

You need to check if of_pmu_irq_cfg is failing.
Is the updated DT picked up correctly ?
Mark Rutland Jan. 11, 2016, 10:39 a.m. UTC | #6
On Sat, Jan 09, 2016 at 07:36:42AM +0100, Dirk Behme wrote:
> On 18.12.2015 11:47, Sudeep Holla wrote:
> >
> >
> >On 18/12/15 10:44, Dirk Behme wrote:
> >>On 18.12.2015 11:16, Sudeep Holla wrote:
> >>>
> >>>
> >>>On 18/12/15 02:29, Simon Horman wrote:
> >>>>From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
> >>>>
> >>>>Enabling the performance monitor unit on r8a7795.
> >>>>
> >>>>Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
> >>>>Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
> >>>>Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
> >>>>Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> >>>>---
> >>>>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
> >>>>  1 file changed, 12 insertions(+)
> >>>>
> >>>>diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> >>>>b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> >>>>index 4d43cf31418f..b9229a49dabc 100644
> >>>>--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> >>>>+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> >>>>@@ -230,6 +230,18 @@
> >>>>              power-domains = <&cpg>;
> >>>>          };
> >>>>
> >>>>+        pmu {
> >>>>+            compatible = "arm,armv8-pmuv3";
> >>>
> >>>Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned
> >>>this
> >>>for some shmobile platform recently.
> >>
> >>
> >>Yes. But as this patch has been applied already to some branches, I
> >>incorporated your a57-pmu hint with an additional update patch:
> >>
> >>http://marc.info/?l=linux-sh&m=145011467914857
> >>
> >>Feel free to squash if still possible.
> >>
> >
> >Ah OK, I didn't know the exact dts name, sorry for the noise.
> >Better if it was posted as part of this series :)
> 
> 
> I finally found some time to test this
> 
> http://marc.info/?l=linux-sh&m=145011467914857
> 
> and surprisingly it doesn't seem to work:
> 
> Using "arm,cortex-a57-pmu" results in
> 
> hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7 counters
> available

This means all the probing logic worked for the A57 PMU.

> hw perfevents: failed to probe PMU!
> hw perfevents: failed to register PMU devices!

These are printed in arm_pmu_device_probe, and following the logic we
must have succesfully allocated the struct pmu, but failed in either
of_pmu_irq_cfg or init_fn (AKA armv8_a53_pmu_init).

In armv8_a53_pmu_init we call armv8pmu_probe_num_events, which will try
to SMP cross-call to an A53 core to probe the number of countesr
implemented. Perhaps the cross-call is failing.

Were the A53s online at this point?

Thanks,
Mark.
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Dirk Behme Jan. 12, 2016, 8:37 a.m. UTC | #7
On 11.01.2016 11:39, Mark Rutland wrote:
> On Sat, Jan 09, 2016 at 07:36:42AM +0100, Dirk Behme wrote:
>> On 18.12.2015 11:47, Sudeep Holla wrote:
>>>
>>>
>>> On 18/12/15 10:44, Dirk Behme wrote:
>>>> On 18.12.2015 11:16, Sudeep Holla wrote:
>>>>>
>>>>>
>>>>> On 18/12/15 02:29, Simon Horman wrote:
>>>>>> From: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>>>>>
>>>>>> Enabling the performance monitor unit on r8a7795.
>>>>>>
>>>>>> Signed-off-by: Masaru Nagai <masaru.nagai.vx@renesas.com>
>>>>>> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
>>>>>> Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
>>>>>> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>>>>> ---
>>>>>>   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
>>>>>>   1 file changed, 12 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> index 4d43cf31418f..b9229a49dabc 100644
>>>>>> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
>>>>>> @@ -230,6 +230,18 @@
>>>>>>               power-domains = <&cpg>;
>>>>>>           };
>>>>>>
>>>>>> +        pmu {
>>>>>> +            compatible = "arm,armv8-pmuv3";
>>>>>
>>>>> Please use arm,cortex-a57-pmu to be more specific. IIRC I mentioned
>>>>> this
>>>>> for some shmobile platform recently.
>>>>
>>>>
>>>> Yes. But as this patch has been applied already to some branches, I
>>>> incorporated your a57-pmu hint with an additional update patch:
>>>>
>>>> http://marc.info/?l=linux-sh&m=145011467914857
>>>>
>>>> Feel free to squash if still possible.
>>>>
>>>
>>> Ah OK, I didn't know the exact dts name, sorry for the noise.
>>> Better if it was posted as part of this series :)
>>
>>
>> I finally found some time to test this
>>
>> http://marc.info/?l=linux-sh&m=145011467914857
>>
>> and surprisingly it doesn't seem to work:
>>
>> Using "arm,cortex-a57-pmu" results in
>>
>> hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7 counters
>> available
>
> This means all the probing logic worked for the A57 PMU.
>
>> hw perfevents: failed to probe PMU!
>> hw perfevents: failed to register PMU devices!
>
> These are printed in arm_pmu_device_probe, and following the logic we
> must have succesfully allocated the struct pmu, but failed in either
> of_pmu_irq_cfg or init_fn (AKA armv8_a53_pmu_init).
>
> In armv8_a53_pmu_init we call armv8pmu_probe_num_events, which will try
> to SMP cross-call to an A53 core to probe the number of countesr
> implemented. Perhaps the cross-call is failing.
>
> Were the A53s online at this point?


Ah, indeed, the A53s failed to run.

Maybe anything like

http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/398773.html

helps to make this more obvious, then?

Thanks!

Best regards

Dirk


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diff mbox

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 4d43cf31418f..b9229a49dabc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -230,6 +230,18 @@ 
 			power-domains = <&cpg>;
 		};
 
+		pmu {
+			compatible = "arm,armv8-pmuv3";
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-affinity = <&a57_0>,
+					     <&a57_1>,
+					     <&a57_2>,
+					     <&a57_3>;
+		};
+
 		timer {
 			compatible = "arm,armv8-timer";
 			interrupts = <GIC_PPI 13