From patchwork Fri Apr 22 23:29:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rich Felker X-Patchwork-Id: 8975511 Return-Path: X-Original-To: patchwork-linux-sh@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A1AD0BF29F for ; Thu, 28 Apr 2016 21:59:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7E8C200C6 for ; Thu, 28 Apr 2016 21:59:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F069320274 for ; Thu, 28 Apr 2016 21:59:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752634AbcD1V7A (ORCPT ); Thu, 28 Apr 2016 17:59:00 -0400 Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:57856 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751534AbcD1V67 (ORCPT ); Thu, 28 Apr 2016 17:58:59 -0400 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1avtxZ-000802-00; Thu, 28 Apr 2016 21:58:57 +0000 Message-Id: In-Reply-To: References: From: Rich Felker Date: Fri, 22 Apr 2016 23:29:13 +0000 Subject: [PATCH 2/7] sh: add AT_HWCAP flag for J-Core cas.l instruction To: linux-sh@vger.kernel.org Cc: Yoshinori Sato Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Rich Felker --- arch/sh/include/uapi/asm/cpu-features.h | 1 + arch/sh/kernel/cpu/sh2/probe.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/sh/include/uapi/asm/cpu-features.h b/arch/sh/include/uapi/asm/cpu-features.h index 694abe4..2f1bc85 100644 --- a/arch/sh/include/uapi/asm/cpu-features.h +++ b/arch/sh/include/uapi/asm/cpu-features.h @@ -22,5 +22,6 @@ #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ +#define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ #endif /* __ASM_SH_CPU_FEATURES_H */ diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index d8dbb81..ecf8360 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -33,6 +33,8 @@ void cpu_probe(void) boot_cpu_data.dcache.entry_shift = 5; boot_cpu_data.dcache.linesz = 32; boot_cpu_data.dcache.flags = 0; + + boot_cpu_data.flags |= CPU_HAS_CAS_L; #else /* * SH-2 doesn't have separate caches