From patchwork Fri Jun 19 11:31:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11613949 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6C1A138C for ; Fri, 19 Jun 2020 11:31:41 +0000 (UTC) Received: by mail.kernel.org (Postfix) id D183C208C7; Fri, 19 Jun 2020 11:31:41 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9DDE6207FC; Fri, 19 Jun 2020 11:31:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DulF29jK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9DDE6207FC Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592566301; x=1624102301; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=UfVOSLTcqF6xKAGoXoeHxnEVgPiigXyHa28boyXOH6Q=; b=DulF29jKQPE7lRn5rBF6lSZIprpifJWbD95fW5Yd5totx6BWqpI36LIF 9FW/cnsB8Q+3z+QGpBMfEOR50oFUhXbArjVx4SIukLMaYm8LuQtBmoOsz Rw6RFXI7OSkk53WMi9QubCOKOnayQ2aMIkC8gJ91jfuKv4LXEImWlW7n1 Nj/Lgz559AntoFPAHeLvVViUyA6OnUb+pOquSsDyaaNpG0Pr3Go/kE+O1 eTcek+yBJ0vs3dYif7YbPv8hvc3O6Pj/Lde0Vt8W+2yyjFC/dt11ekHMx 8W0LVufR4WNDvfnGTQpfOdeolq/xFA0m88Vtw9w/W7OdWUDKEeGKC6hZf w==; IronPort-SDR: OC/IJX71ViysRevrfGLlaWcMy5Nz1nSqUhqRmG9vQjTkpyGFoX5wfRZGRLk0ZSps4TDWUYMd5g w0312+f0izYSgJgl4K3gm9PrWhV90FhwXMPC0QHKlJNgFQmg2WwsQ27tc9twYFRJLGa8XvsAN3 GMAHXJcOlF9G6b5guyyz15UgAz15ZJucXxDD1SoZIqsRStNwZR1+A9ZSeGRbIjQknL4khuw90X rlRvojNCLunFOFFbh1+uIGODUaW3SNv5xd63EBOkksGBpBOxjlWvIaGbeJYE75eZxaOzHeGg7c j0c= X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="84298522" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Jun 2020 04:31:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 19 Jun 2020 04:31:26 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 04:31:24 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Serge Semin , Serge Semin Subject: [PATCH v2 0/6] spi: Adding support for Microchip Sparx5 SoC Date: Fri, 19 Jun 2020 13:31:15 +0200 Message-ID: <20200619113121.9984-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 This is an add-on series to the main SoC Sparx5 series (Message-ID: <20200615133242.24911-1-lars.povlsen@microchip.com> The series add support for the Sparx5 SoC SPI controller in the spi-dw-mmio.c spi driver. v2 changes: - Moved all RX sample delay into spi-dw-core.c, using the "snps,rx-sample-delay-ns" device property. - Integrated Sparx5 support directly in spi-dw-mmio.c - Changed SPI2 configuration to per-slave "microchip,spi-interface2" property. - Added bindings to existing snps,dw-apb-ssi.yaml file - Dropped patches for polled mode and SPI memory operations. Lars Povlsen (6): spi: dw: Add support for RX sample delay register arm64: dts: sparx5: Add SPI controller spi: dw: Add Microchip Sparx5 support dt-bindings: snps,dw-apb-ssi: Add sparx5, SPI slave snps,rx-sample-delay-ns and microchip,spi-interface2 properties. arm64: dts: sparx5: Add spi-nor support arm64: dts: sparx5: Add spi-nand devices .../bindings/spi/snps,dw-apb-ssi.yaml | 24 ++++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 34 ++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 16 +++ .../boot/dts/microchip/sparx5_pcb134.dts | 22 ++++ .../dts/microchip/sparx5_pcb134_board.dtsi | 9 ++ .../boot/dts/microchip/sparx5_pcb135.dts | 23 ++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 9 ++ drivers/spi/spi-dw-core.c | 20 ++++ drivers/spi/spi-dw-mmio.c | 113 +++++++++++++++++- drivers/spi/spi-dw.h | 2 + 10 files changed, 271 insertions(+), 1 deletion(-) --- 2.27.0