From patchwork Wed Jul 8 17:50:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11652061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D97E912 for ; Wed, 8 Jul 2020 17:50:43 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 08222206F6; Wed, 8 Jul 2020 17:50:43 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8431206E9; Wed, 8 Jul 2020 17:50:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8431206E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: pci2QpIUvqfH0keklntns8mgo+AU/DcIgXsAHE4TmNEmjCynJGSdYoOzx4vz9IWtTrgShUZHJT pOADkSgnNCFw== X-IronPort-AV: E=McAfee;i="6000,8403,9676"; a="209405778" X-IronPort-AV: E=Sophos;i="5.75,328,1589266800"; d="scan'208";a="209405778" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 10:50:42 -0700 IronPort-SDR: VZ9GFeLDbkCynhnB5XBEGm94Mvjvl1gYqGh27J3Q+nnaOJKZVqiFBxTOrYUGUBjM4C+CELdZNk Qwm2XnLrr86w== X-IronPort-AV: E=Sophos;i="5.75,328,1589266800"; d="scan'208";a="457591788" Received: from sgyanama-mobl1.gar.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.5.67]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 10:50:37 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Jassi Brar , Arnd Bergmann , Olof Johansson Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Dinh Nguyen , Paul Murphy , Will Deacon , Daniele Alessandrelli Subject: [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Date: Wed, 8 Jul 2020 18:50:15 +0100 Message-Id: <20200708175020.194436-1-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Hi, This patch-set adds initial support for a new Intel Movidius SoC code-named Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This initial patch-set enables only the minimal set of components required to make the Keem Bay EVM board boot into initramfs. Changes from v1 to v2: * Moved keembay-scmi-mailbox driver to a separate patchset * Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree Regards, Daniele Daniele Alessandrelli (5): arm64: Add config for Keem Bay SoC dt-bindings: arm: Add Keem Bay bindings MAINTAINERS: Add maintainers for Keem Bay SoC arm64: dts: keembay: Add device tree for Keem Bay SoC arm64: dts: keembay: Add device tree for Keem Bay EVM board .../devicetree/bindings/arm/keembay.yaml | 19 ++ MAINTAINERS | 10 + arch/arm64/Kconfig.platforms | 5 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/keembay-evm.dts | 39 ++++ arch/arm64/boot/dts/intel/keembay-soc.dtsi | 125 ++++++++++++ include/dt-bindings/clock/keembay-clocks.h | 188 ++++++++++++++++++ include/dt-bindings/power/keembay-power.h | 19 ++ 8 files changed, 406 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi create mode 100644 include/dt-bindings/clock/keembay-clocks.h create mode 100644 include/dt-bindings/power/keembay-power.h