From patchwork Fri Jul 26 11:03:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 13742630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 697B0C3DA7F for ; Fri, 26 Jul 2024 11:09:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 50310C4AF14; Fri, 26 Jul 2024 11:09:13 +0000 (UTC) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 56F79C4AF07; Fri, 26 Jul 2024 11:09:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 56F79C4AF07 Authentication-Results: smtp.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 26 Jul 2024 19:03:56 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 26 Jul 2024 19:03:56 +0800 From: Kevin Chen List-Id: To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 00/10] Introduce ASPEED AST27XX BMC SoC Date: Fri, 26 Jul 2024 19:03:45 +0800 Message-ID: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 This patchset adds initial support for the ASPEED. AST27XX Board Management controller (BMC) SoC family. AST2700 is ASPEED's 8th-generation server management processor. Featuring a quad-core ARM Cortex A35 64-bit processor and two independent ARM Cortex M4 processors This patchset adds minimal architecture and drivers such as: Clocksource, Clock and Reset This patchset was tested on the ASPEED AST2700 evaluation board. Kevin Chen (10): dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock clk: ast2700: add clock controller dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset dt-bindings: arm: aspeed: Add maintainer dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string arm64: aspeed: Add support for ASPEED AST2700 BMC SoC arm64: dts: aspeed: Add initial AST27XX device tree arm64: dts: aspeed: Add initial AST2700 EVB device tree arm64: defconfig: Add ASPEED AST2700 family support .../bindings/arm/aspeed/aspeed.yaml | 6 + .../bindings/mfd/aspeed,ast2x00-scu.yaml | 3 + MAINTAINERS | 3 + arch/arm64/Kconfig.platforms | 14 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/Makefile | 4 + arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 217 +++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 50 + arch/arm64/configs/defconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/clk-ast2700.c | 1166 +++++++++++++++++ .../dt-bindings/clock/aspeed,ast2700-clk.h | 180 +++ .../dt-bindings/reset/aspeed,ast2700-reset.h | 126 ++ 13 files changed, 1772 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts create mode 100644 drivers/clk/clk-ast2700.c create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h