From patchwork Thu Feb 27 18:22:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 75D4514D5 for ; Thu, 27 Feb 2020 18:22:40 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CCCA246B4 for ; Thu, 27 Feb 2020 18:22:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="r20Z4zz/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4CCCA246B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1489+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id hDOMYY1556264x0nNwxegyD3; Thu, 27 Feb 2020 10:22:40 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web09.151.1582827759871058380 for ; Thu, 27 Feb 2020 10:22:39 -0800 X-Received: by mail.kernel.org (Postfix) id A8DCE246AE; Thu, 27 Feb 2020 18:22:39 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 6BE53246A6; Thu, 27 Feb 2020 18:22:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6BE53246A6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36C2730E; Thu, 27 Feb 2020 10:22:39 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8C2B13F73B; Thu, 27 Feb 2020 10:22:37 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 10/13] dt-bindings: memory-controllers: Convert Calxeda DDR to json-schema Date: Thu, 27 Feb 2020 18:22:07 +0000 Message-Id: <20200227182210.89512-11-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: fpwD1zC4n84jm1FjhGyEQ0mmx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827760; bh=p/mlfq9Q4wKFtZQvlbqlEXgDXVXlp8Y8KAp3nU/TUXQ=; h=Cc:Date:From:Reply-To:Subject:To; b=r20Z4zz/XAmRnh/f2mjpDhsCTtOo1bFCGG71/O4S13bXwLjYUQLad8IxuGTZZYFKcdD q51oHKEsgWZG/c5qgBqJqfKNRbxDi/eos2XSwn88VRTi/FE+dMkiWe7bdLdlsF82wNFc5 CP/LnqZAlZeOCBoGnGh8ySx7yiAZRsHbUlw= Convert the Calxeda DDR memory controller binding to DT schema format using json-schema. Although this technically covers the whole DRAM controller, the intention to use it only for error reporting and mapping fault addresses to DRAM chips. Signed-off-by: Andre Przywara --- .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 ------- .../memory-controllers/calxeda-ddr-ctrlr.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt deleted file mode 100644 index 049675944b78..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt +++ /dev/null @@ -1,16 +0,0 @@ -Calxeda DDR memory controller - -Properties: -- compatible : Should be: - - "calxeda,hb-ddr-ctrl" for ECX-1000 - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 -- reg : Address and size for DDR controller registers. -- interrupts : Interrupt for DDR controller. - -Example: - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml new file mode 100644 index 000000000000..d9739501d61d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda DDR memory controller binding + +description: | + The Calxeda DDR memory controller is initialised and programmed by the + firmware, but an OS might want to read its registers for error reporting + purposes and to learn about the DRAM topology. + +maintainers: + - Andre Przywara + +properties: + compatible: + enum: + - calxeda,hb-ddr-ctrl + - calxeda,ecx-2000-ddr-ctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + };