From patchwork Fri Mar 27 12:44:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: afzal mohammed X-Patchwork-Id: 11462347 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B36413A4 for ; Fri, 27 Mar 2020 12:44:31 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 05D6E20838; Fri, 27 Mar 2020 12:44:31 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D7122206F2; Fri, 27 Mar 2020 12:44:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GIA92C3G" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D7122206F2 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=afzal.mohd.ma@gmail.com Received: by mail-pg1-f193.google.com with SMTP id b1so4514240pgm.8; Fri, 27 Mar 2020 05:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OrmCqFezly2Rfxgtc8/QFu/0W5F3zvpkrW43juhNMPA=; b=GIA92C3GyqkFnDX8sA9Rknn8fwTnET1ETunHwCgySE9vDZlgyPZM1GTEDiX4Ed9drc YH4plfCR6mDkoPfE0nOfFfGPjfLT+W2/okVZ5EhQ+LPZD+3k3spQS23pLTXBiYuvPVjx o87eiA3EwHWieUIzUz0Xe1Up70BMgfdBO+fHkji+RKnEtXlrpr8/rOeK064Y/AmaDTya RcA9Vm3DNDRleceqduZA8aNk0u38lr/33qFn8a+ay0hVHF40ghOEWJqr4PkbpBpSavrW ZKpgwHZ525bKABBbRN8QEulmTk7qyiRpqA+dN3IRCfA+WZ+NBdJSPtEJ3DFpcz4HCpN+ r5Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OrmCqFezly2Rfxgtc8/QFu/0W5F3zvpkrW43juhNMPA=; b=KvxfBEvAAmaZ+NVXIEfUGlwokPR8ONvT8d68pSAvAVkBZnZT5AzHQKZYEM26FoDBeO UDnL4a4Z+/lAHnbAv+CdA3N5j9emT0xi/KtWkW97sGVQPcfPr9VnHk+vzUt1xIXpHKdQ HDIikoO54tEdQofSBQASkmrb8LJK3+qtbk4pE3jX5nGm1Vrfl+5eu0Wgwix22aMnk9AJ 6FmHHMAB7z2/ftddmzOOHXGAcLXtkUV8KNQ++C6UCqNgw8ppJ1pbLBs2TvZnpajQF9JE dZvFTCzAEgVBL8BnWufVkb0OyQM1jkBq5MiRpefhdroDvOAGDh5XA5aK5P+hCbtM2xgp fWRA== X-Gm-Message-State: ANhLgQ0IV7ucGmWExnXRZLO3t31Gpc95CyLGjFdXvxp+UBEFz34uxEND ZKIrY+WyUp88HIqrxhaHhD8= X-Google-Smtp-Source: ADFU+vv89RkFVcocDRn4TLjad8m0Ax5S8FfzmE4pizTzzOO9MsncIbmfrgyhAIrDyE9xef9gEK/Cfg== X-Received: by 2002:a62:6503:: with SMTP id z3mr14798534pfb.232.1585313070409; Fri, 27 Mar 2020 05:44:30 -0700 (PDT) Received: from localhost.localdomain ([49.207.51.33]) by smtp.gmail.com with ESMTPSA id u129sm4070380pfb.101.2020.03.27.05.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2020 05:44:29 -0700 (PDT) From: afzal mohammed List-Id: To: Arnd Bergmann , SoC Team Cc: afzal mohammed , Thomas Gleixner , Tony Lindgren , Alexander Sverdlin , =?utf-8?q?Krzysztof_Ha?= =?utf-8?q?=C5=82asa?= , Viresh Kumar , Lubomir Rintel , Gregory CLEMENT , Hartley Sweeten , Viresh Kumar , Shiraz Hashim , Andrew Lunn , Jason Cooper , Sebastian Hesselbarth , Russell King , Linux ARM , "linux-kernel@vger.kernel.org" , arm-soc , Olof Johansson Subject: [PATCH v4 3/5] ARM: cns3xxx: replace setup_irq() by request_irq() Date: Fri, 27 Mar 2020 18:14:22 +0530 Message-Id: <20200327124422.4181-1-afzal.mohd.ma@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: References: request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Signed-off-by: afzal mohammed Acked-by: Krzysztof Halasa --- v4: * Add received tags v3: * Split out from series, also split out from ARM patch to subarch level as Thomas suggested to take it thr' respective maintainers * Modify string displayed in case of error as suggested by Thomas * Re-arrange code as required to improve readability * Remove irrelevant parts from commit message & improve v2: * Replace pr_err("request_irq() on %s failed" by pr_err("%s: request_irq() failed" * Commit message massage arch/arm/mach-cns3xxx/core.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 1d61a7701c11..e4f4b20b83a2 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -189,12 +189,6 @@ static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction cns3xxx_timer_irq = { - .name = "timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .handler = cns3xxx_timer_interrupt, -}; - /* * Set up the clock source and clock events devices */ @@ -245,7 +239,9 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq) writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); /* Make irqs happen for the system timer */ - setup_irq(timer_irq, &cns3xxx_timer_irq); + if (request_irq(timer_irq, cns3xxx_timer_interrupt, + IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL)) + pr_err("Failed to request irq %d (timer)\n", timer_irq); cns3xxx_clockevents_init(timer_irq); }