From patchwork Wed May 13 12:55:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11545979 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 818E1112C for ; Wed, 13 May 2020 12:56:27 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 7C534206E5; Wed, 13 May 2020 12:56:27 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 327EA206D6; Wed, 13 May 2020 12:56:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1u1xnpu1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 327EA206D6 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374587; x=1620910587; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WZs4qSGRBrl6o2f2lxXITxeDdZF+Q5jzpsB7ABIsFbU=; b=1u1xnpu1gKMXcyO0X1jpeihSzw0BMZmgsoTfMWuo9IZbVXjAN2eQle3W H5NrAWHzWf71f4MMGXMQNCqynhI6P6/bBe3VA0K9eH6QKa0hSfsszqSIb z/DW5QAFPkrCrmFygccMLc0M77VaI+hOaje8EEO+VXrFrkK8VnK52QQE8 RrcnZ9W0Xr0IJRmsc000W7qkRpe7xba7VomCIJUDJcrUdFbTJP+AzPSCp vpZE8VO1IP+GGOhLyeZ2bQyopWpue4XBTeMdTQ78dgtNGt076Jrn1G1YT 3ihL68w6fSpQIAZK640b9Glf9YYbCYnw+2zDdVDYKQEnkVe2Y3aOvJ6PX g==; IronPort-SDR: 3ikZKAyB22KBrZk1FzU8VvJgBhd9k54O9JjFg6AcKl3y9Du84qZFtlR0mm7ZAHBquLWsOmxT2R xnpvkU5ljUwcmRcU0VIqdmxBlHmLDgerCJwSFXxz+8XqAmRUrCA6AYOm0Vx1W0gX6HKE1Umtfp wW+iNZ6sTV/7rFMhhZ1LWtri18WBwwgMKdDswvBQl4vPatwlGTrb3PhXSOKItooUNrZcudLsQt xX8TgWneIZeWwb8SKPjaGpDbbgsuO85ZfHWrw9egM7BuaczTqN8V0XyD+FZmsByL3sys6mIrpb waw= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132769" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:26 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:28 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:23 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 03/14] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 Date: Wed, 13 May 2020 14:55:21 +0200 Message-ID: <20200513125532.24585-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This fixes a problem with using the GPIO as an interrupt on Jaguar2 (and similar), as the register layout of the platforms with 64 GPIO's are pairwise, such that the original offset must be multiplied with the platform stride. Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/pinctrl/pinctrl-ocelot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 375f3ea3b80c4..95c225bc7572f 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -680,11 +680,12 @@ static void ocelot_irq_handler(struct irq_desc *desc) struct irq_chip *parent_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; unsigned int reg = 0, irq, i; unsigned long irqs; for (i = 0; i < info->stride; i++) { - regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®); + regmap_read(info->map, id_reg + 4 * i, ®); if (!reg) continue;