From patchwork Wed May 13 12:55:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11545981 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7BC8112C for ; Wed, 13 May 2020 12:56:34 +0000 (UTC) Received: by mail.kernel.org (Postfix) id C24272492D; Wed, 13 May 2020 12:56:34 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6FEC0206D6; Wed, 13 May 2020 12:56:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DqLhtCfC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6FEC0206D6 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589374594; x=1620910594; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XzyAjS+VdICD+VDbBl+tF57k++B6rYPYjva3OeaJ/X8=; b=DqLhtCfCJn8E1zhcSijsNdJvAaJwDGh4ptZuGznl5fITeNH9NOnj0aje oXM+DjmdezJNEj7gzaNBTHmVqAwTnhSAYRaBFDqQHptti/5Yl/9T7CITB ZMshRg3z1OTfbz5RWDF1Ipj4zHNzNcl9WMdRRrr669CPqX9RTCYBNPTsZ JTwCDoxVgwFmR7fyUtpODYLRiSjcrGuQEFebzICDDxe/g7RHsF4fEcIF1 ihZTWujlnUSxoF9p1B31+jF+8qCJ4+YVCHgfoT39voeZgeSRpCZCI5bOZ ewIG2hxH+hd802kbIKzzZ6gwEXvCu73UJLBxN/gEAb5daeT9UcUuBpy30 g==; IronPort-SDR: JwLwlM1erNzBBGrUO3T1+ZqDwN8fhRVhDgIwzSxlGBJtM46S/CKnrYo4HkoV/lOh6UzB2CqgAu a4xgKEkrsGAhVgDYrbv6HCfdIGBxKv/tUn0OKhb8cHQj0bUWBWnDwRI0DyO/bs3Lu8HCffr4Re I2ZgrNSvM5UF2ub5WOoWyPliNeAYMKom1MVzcuFN3zeJBWDssIa3fvY6Vc4AICcjOfNxlWtaNY KsKGX3TX+AxoU54N/faoOMEmT6yWR08YKHYD521JoOMg+VJ+m6vCeVKeNMTNXVDb3j7PkR/9ZS 3tc= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75132778" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 05:56:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 05:56:33 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 05:56:30 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH 04/14] arm64: sparx5: Add support for Microchip 2xA53 SoC Date: Wed, 13 May 2020 14:55:22 +0200 Message-ID: <20200513125532.24585-5-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com> References: <20200513125532.24585-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- MAINTAINERS | 8 ++++++++ arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 2 files changed, 22 insertions(+) -- 2.26.2 diff --git a/MAINTAINERS b/MAINTAINERS index 091ec22c1a23f..1b5a18d3dbb9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2079,6 +2079,14 @@ X: drivers/net/wireless/atmel/ N: at91 N: atmel +ARM/Microchip Sparx5 SoC support +M: Lars Povlsen +M: Steen Hegelund +M: Microchip Linux Driver Support +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +N: sparx5 +S: Supported + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 55d70cfe0f9e1..e1734a13a967b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,20 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_SPARX5 + bool "ARMv8 based Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select PM_GENERIC_DOMAINS if PM