From patchwork Wed May 13 13:08:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F11F81 for ; Wed, 13 May 2020 13:09:02 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 58C72206B7; Wed, 13 May 2020 13:09:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A02F20673; Wed, 13 May 2020 13:09:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KtfiAULL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A02F20673 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589375342; x=1620911342; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ykGNljrOL3uL7TOqwtHYrU0bzI70hpjkW9oijaZnkD4=; b=KtfiAULLQbcvn6U0FW/C4zLxARwV1dZMCeL1LfdIGXhXNiy5oI16I9BY pprB7kOOvAD6iQBudCa+/k7xaoXF8E1yf8/kQFjzzycvy8qlYjx2DuPFE mRoL3IMQU/vv4mQQhtOeDdZ2FVbQbmpk5DCofJwyQWJJhYwJqhJTlPMnj tPjdeFN16U452Qp0EpNUd/n8F3OMWNokvAYdvtO+zczCme5f0jzevZueb mlMDdn/4I9Ah4gVW6j0dMASG6kmaC3pETJDlk5qzLrnzwa7hOI+3OhbUE Opblci67Ei/Dm31olum1GkjQZq4r4I8kOJqdBM+/fimRaaSZqGY3J7NEe A==; IronPort-SDR: pp4CAtxiOJ18bIMjqxiPSRdDrgZcaeMpLz8CbXkSO+KTloXEVNF1IHYP6QlO1fwOxxW5mRXd1s HgqbGO1XEwzb3Wn4qNWElxT+rKYtCLtm9QW9bJkcSHdWJ28KMwovk+0Bn5UoEp4pMb+NLdkoeW /LPDUWLUlLoSnARibPtUAA9QsYq9iWa5rWzlVyWIt/u0UpGjIYEaJcEVZj7mqz2cY0D0emTBQ5 JhBdFIkuo3ZrA0v7ONMMUJa1UpHO6N0OPGIBs3hCx7E1YqaLjsY85HTxEl6gcIbXEemXJk7Rgk CX0= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76497693" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:08:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:08:59 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:08:54 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team , Rob Herring CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 1/5] dt-bindings: reset: ocelot: Add Sparx5 support Date: Wed, 13 May 2020 15:08:38 +0200 Message-ID: <20200513130842.24847-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com> References: <20200513130842.24847-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds the support for the Sparx5 SoC. Signed-off-by: Lars Povlsen --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++-- MAINTAINERS | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 1b4213eb34731..4d530d8154848 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -1,10 +1,13 @@ Microsemi Ocelot reset controller The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. +SoC core. + +The reset registers are both present in the MSCC vcoreiii MIPS and +microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" + - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { diff --git a/MAINTAINERS b/MAINTAINERS index 5aa28d6e39d4f..1db598723a1d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11230,6 +11230,7 @@ M: Microchip Linux Driver Support L: linux-mips@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt +F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c