From patchwork Mon Jun 15 13:32:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11605053 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E63AE618 for ; Mon, 15 Jun 2020 13:33:29 +0000 (UTC) Received: by mail.kernel.org (Postfix) id E0934208FE; Mon, 15 Jun 2020 13:33:29 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa6.microchip.iphmx.com (esa6.microchip.iphmx.com [216.71.154.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A63B420882; Mon, 15 Jun 2020 13:33:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="fpDLtFCx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A63B420882 Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592228009; x=1623764009; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pq7+Cad0Upf0gR5pSZeWVklhIYbcWc/Z2/yeAnUUmgY=; b=fpDLtFCx/Jv/9FBAr5z4aCyxpCVoyPZZVFt1A0Vlr4kCTaKz020soRxD n38SX6xSsGO94bATIsoHG0dgacApGKWzzwWSkgYjdFfxBu/ML7JA4Q14k YWOeUFfdhSLeu1WNKrYRwzeMIJRfv7UAtSTvTr12Z2NnRwFgNU+lbgAiU 73CWgmOd9HNdmibblF9WesTP5vZsS601Rd/j9+HXsP2JefILqLa9E6NcQ UkVow9vzBHtha+x/vTvQ0jMKq4wbJXR5LKfIWibxbzP/sPcnKHv3oOg18 BAfJa7YtzRyoG6OsMsyv/RiJKjjTd0J5jkcD9m7VFowchufeMT8yyE1gw g==; IronPort-SDR: FJq1dMJI7LFLn52yKCI4CKrNZiG6i7Sm9giGAEhs/bVB0SewWfe7/PoRUA/fXDL9TBeGYWzisc YikhRiOl+0k/r3hzLODMcL6ZPd2jtMCp415K/YWsdQCzcswxDL5a1qSNPWN2bGwoH2BuTy8RrL GjOsPGH3HRJL7qfnlWo8BLfpUyEvS3btrLrQfcpeq9BAXG8hLjVWUAD7wzwZLchNspqGOT+shw YApGwLj/7mNu2/lIBXMO5ioEcdnfZYQMtrgexxEhHBbkqVfFWYI4MC8eNSmio7Kl5+eFgLSZhf dJ8= X-IronPort-AV: E=Sophos;i="5.73,514,1583218800"; d="scan'208";a="15805535" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Jun 2020 06:33:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 15 Jun 2020 06:33:28 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 15 Jun 2020 06:33:25 -0700 From: Lars Povlsen List-Id: To: SoC Team , Arnd Bergmann , Stephen Boyd , Linus Walleij CC: Lars Povlsen , Steen Hegelund , Microchip Linux Driver Support , Olof Johansson , "Michael Turquette" , , , , , , Alexandre Belloni Subject: [PATCH v3 09/10] arm64: dts: sparx5: Add Sparx5 SoC DPLL clock Date: Mon, 15 Jun 2020 15:32:41 +0200 Message-ID: <20200615133242.24911-10-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200615133242.24911-1-lars.povlsen@microchip.com> References: <20200615133242.24911-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 39 +++++++++++++---------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index baf4176ce1dfe..161846caf9c94 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -72,20 +72,29 @@ timer { ; }; - clocks: clocks { - #address-cells = <2>; - #size-cells = <1>; - ranges; - ahb_clk: ahb-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - sys_clk: sys-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <625000000>; - }; + lcpll_clk: lcpll-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000000>; + }; + + clks: clock-controller@61110000c { + compatible = "microchip,sparx5-dpll"; + #clock-cells = <1>; + clocks = <&lcpll_clk>; + reg = <0x6 0x1110000c 0x24>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; }; axi: axi@600000000 { @@ -161,8 +170,6 @@ uart2_pins: uart2-pins { pins = "GPIO_26", "GPIO_27"; function = "uart2"; }; - }; - }; };