From patchwork Thu Jun 18 14:13:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11612295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 471D4138C for ; Thu, 18 Jun 2020 14:14:01 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 40E3F207E8; Thu, 18 Jun 2020 14:14:01 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03A8720739 for ; Thu, 18 Jun 2020 14:14:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="eeLzJOe0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03A8720739 Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592489640; x=1624025640; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xXlRuWDsgHzsC/cK9WaU+YzlpcD2wIPLoPF5OvjRa5Y=; b=eeLzJOe09Qz4Y+cBG6qxXPhDXnGtZDkSg+zDSVpGCzdC1NePZGoHKi6n m1fPySNuB/IgkFJT2UhCxL/CEtZ+FqZTqd8CUjkduZh7dC9cIc+h40z9p GalekisjQYXibDrs5il4p50fojof5UGHAMDgzFTRhLPvXoBqcdn7zJ4uw gDXnmpnAKC/vy1nGYfe6wPhKsTxUZmzKABxpe2VqB6zzQy3A36ngEEpvs qGulrVr5Ar8u9vriWB6xBJVriMi4UJGQpVI4EMtSd2RChoWIEUsW+O09G WCNc4QbQ3KJn6CuOnKjJxCjwNLIUAZDf2lsQFGEcDeIDp4t0CHwvw+q+X Q==; IronPort-SDR: 35EFXpDv5rWakdQUkUCRxWM0ZzuOx/gfmCp8J5dvbSiaJVvcaUDiePTZzz7EKzfJh3P3+l7+1c 08B/l+nSGHojSCwVCtPwoBAY6U6kkdEdGJvAPpj1rgjsLmOlwbNGxRd1IFWOrn/Wg9sb15YQ1K Lo6j14ILgBTdNeAmoivvQ0MDuhUhTpvrQvCT53gwGPLF5cpIcMCGeHWCCx6zhLk1KVMuCpd4jM /aU+1QMhH1ZXjAsfP0IO5+a781yk7yQNpX+z16el6OUcvI051iKWaYKhpeF1thtvFvIXnLoXRO xL0= X-IronPort-AV: E=Sophos;i="5.73,526,1583218800"; d="scan'208";a="78953903" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Jun 2020 07:14:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 18 Jun 2020 07:13:53 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 18 Jun 2020 07:13:51 -0700 From: Lars Povlsen List-Id: To: Ulf Hansson , Adrian Hunter , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH v4 3/3] arm64: dts: sparx5: Add Sparx5 eMMC support Date: Thu, 18 Jun 2020 16:13:26 +0200 Message-ID: <20200618141326.25723-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200618141326.25723-1-lars.povlsen@microchip.com> References: <20200618141326.25723-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 +++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 23 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 84bca999420ef..c9dbd1a8b22b6 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { compatible = "microchip,sparx5"; @@ -162,6 +163,20 @@ timer1: timer@600105000 { interrupts = ; }; + sdhci0: sdhci@600800000 { + compatible = "microchip,dw-sparx5-sdhci"; + status = "disabled"; + reg = <0x6 0x00800000 0x1000>; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + clocks = <&clks CLK_ID_AUX1>; + clock-names = "core"; + assigned-clocks = <&clks CLK_ID_AUX1>; + assigned-clock-rates = <800000000>; + interrupts = ; + bus-width = <8>; + }; + gpio: pinctrl@6110101e0 { compatible = "microchip,sparx5-pinctrl"; reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; @@ -191,6 +206,15 @@ i2c2_pins: i2c2-pins { pins = "GPIO_28", "GPIO_29"; function = "twi2"; }; + + emmc_pins: emmc-pins { + pins = "GPIO_34", "GPIO_35", "GPIO_36", + "GPIO_37", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + function = "emmc"; + }; }; i2c0: i2c@600101000 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 91ee5b6cfc37a..573309fe45823 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -16,6 +16,29 @@ memory@0 { }; }; +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; + pinctrl-0 = <&emmc_pins>; + max-frequency = <8000000>; + microchip,clock-delay = <10>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts index 10081a66961bb..bbb9852c1f151 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -15,3 +15,26 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts index 741f0e12260e5..f82266fe2ad49 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -15,3 +15,26 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +};