From patchwork Fri Jun 19 11:31:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11613957 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E4FC1731 for ; Fri, 19 Jun 2020 11:31:44 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 2819920FC3; Fri, 19 Jun 2020 11:31:44 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa4.microchip.iphmx.com (esa4.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CCF0C207FC; Fri, 19 Jun 2020 11:31:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="x3InQ6yT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CCF0C207FC Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592566303; x=1624102303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=19MOvcR0nsnDT3YcIrCLwDvMaCViNOXGoQ4rVMNBvY4=; b=x3InQ6yTp58K3tSvWu9JgCuvh0mHKr7YfzT2b/164tZIcWirwrKTM5M8 e09QraQUFkBnGRkUfkCaeIFsUrGkeV1WfoGg2OOFv9YvDtO440gZuYy0s 3an+2Ykkmo9wTveEYPAjlXUlqWWtMhcSm6DDEtDagbzGxx1nXQIfwqECD ukKruXk/G8I+OZbGLU0AQaLMyFwatA5RHVhveA0BAkaXzPoef1KDMERs/ JEOnNdTwIPYn6k2z8uQnpehn8y0knzeVrNjLSY8UBkLfkiU+KAO+lIh5W 9BbsEOJiKDBwqMY0kYyKlU2CvFDKP/xCvlOwdqS7v9+1hV1m/mbW2SzLl A==; IronPort-SDR: 4/WxqRybhw55PExWHGU3OtD0Qo5/Em9m9d04aQhoExdrQpP6eUWA5wEoCVpw/t8voZLxwrZJMF R1MQAKHfHNC9x6w77HA5QieZl160Qu3Fhq2EZKgmcErKBfv3/rnCDVlXAqA+KhAVd0MYjrKoEI paAfOTjbbTszwLBGUky9JGq18C7OTQQ1sThBdLCWMSQBqXP+yFSKcpdYLz5+x+l2QSpb9Mc5Sx LtYx7OSwJVLAS1VRPnrZOhh8Rt9BWlVoIIUBehTN8FaWxm/dzzDXNpc+MkvEzTxpPqobsYKQNM 2jw= X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="77162027" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Jun 2020 04:31:42 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 19 Jun 2020 04:31:35 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 04:31:33 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team , Rob Herring CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Serge Semin , Serge Semin Subject: [PATCH v2 4/6] dt-bindings: snps,dw-apb-ssi: Add sparx5, SPI slave snps,rx-sample-delay-ns and microchip,spi-interface2 properties. Date: Fri, 19 Jun 2020 13:31:19 +0200 Message-ID: <20200619113121.9984-5-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619113121.9984-1-lars.povlsen@microchip.com> References: <20200619113121.9984-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This has the following changes for the snps,dw-apb-ss DT bindings: - Add "microchip,sparx5-spi" as the compatible for the Sparx5 SoC controller, - Add the property "snps,rx-sample-delay-ns" for SPI slaves - Add the property "microchip,spi-interface2" for SPI slaves Signed-off-by: Lars Povlsen --- .../bindings/spi/snps,dw-apb-ssi.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.27.0 diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index c62cbe79f00dd..5bca4f0493bdf 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -36,6 +36,11 @@ properties: - mscc,ocelot-spi - mscc,jaguar2-spi - const: snps,dw-apb-ssi + - description: Microchip Sparx5 SoC SPI Controller + items: + - enum: + - microchip,sparx5-spi + - const: snps,dw-apb-ssi - description: Amazon Alpine SPI Controller const: amazon,alpine-dw-apb-ssi - description: Renesas RZ/N1 SPI Controller @@ -107,6 +112,19 @@ patternProperties: spi-tx-bus-width: const: 1 + snps,rx-sample-delay-ns: + description: SPI Rx sample delay offset, unit is nanoseconds. + The delay from the default sample time before the actual + sample of the rxd input signal occurs. The "rx_sample_delay" + is an optional feature of the designware controller, and the + upper limit is also subject to controller configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + + microchip,spi-interface2: + description: indicates the spi device is placed on a special + controller interface of the "microchip,sparx5-spi" controller. + type: boolean + unevaluatedProperties: false required: @@ -129,5 +147,11 @@ examples: num-cs = <2>; cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; + spi-flash@1 { + compatible = "spi-nand"; + reg = <1>; + microchip,spi-interface2; + snps,rx-sample-delay-ns = <7>; + }; }; ...