From patchwork Fri Jun 19 11:31:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11613959 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 180C8138C for ; Fri, 19 Jun 2020 11:31:46 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 125F62083B; Fri, 19 Jun 2020 11:31:46 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC6A9207FC; Fri, 19 Jun 2020 11:31:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="prKmWmHa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DC6A9207FC Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1592566305; x=1624102305; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p+8RoWLbgzQ96coLA+SJ/+5qhlXapbbgZpZg9wtUuf4=; b=prKmWmHaPHsIQ3mH0SoTiChHtahOazQX7Vv5gN4dp90nPk+pndnSVnQh Ly1OjIsICWf/KY5/I/qlRSXL4RqbWzMI0/Flnjtd7hjMoX3+M/fGcSRoU Vc1He8uAObXTT/QwE0tY/l03wjVpDpcu6DN5tixd6GNGtPzFRKdT6wtfj nBHnT6DszWZrBiSXxc6JBFCrjy8CCUw2wC4oh+eSa6xdNhDHfd/hePMSJ 10qOyRNdcYxWSG85+2PBsEi0va6TnLc+RBg96I4XF/JXtXpfDWHTHQ6XN 4ww8Ml4VAIhC6NTrViizhKPRzHjBVgCn9JVtThT6BDGc84VH/qP04G/P7 w==; IronPort-SDR: 7kjYpE4qCwU7hpIjsZCmnRIAd63u0JaCTHfE16IVpCjaQ2e6/R8xLUWIuAK4TWhSkZMVlPBqUx k/J21FbffWBfXn9Lyq+n+lrdD+MFdotgtghkdXt9jJE1iJEKpVa7Y1Xo/WVcLR/nEhtDcadQ6A 64zHnZLFZQPRgDD4ukTi/TJTK0TYQqGVUdaHWFruG7I+rPWADwZjcQuAam79wLfsQTlqIaLcs9 SN6CxnQ50EAExGTADKCK9Fy/8NUWjQgrkjKOaPwa7Mx1UvYxSVnfvaURqLEe9r5oh0AQP4kG/Q fWU= X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="84298554" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Jun 2020 04:31:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 19 Jun 2020 04:31:45 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 04:31:35 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Serge Semin , Serge Semin Subject: [PATCH v2 5/6] arm64: dts: sparx5: Add spi-nor support Date: Fri, 19 Jun 2020 13:31:20 +0200 Message-ID: <20200619113121.9984-6-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619113121.9984-1-lars.povlsen@microchip.com> References: <20200619113121.9984-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 9 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 9 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 573309fe45823..d8b5d23abfab0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -39,6 +39,15 @@ &sdhci0 { microchip,clock-delay = <10>; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 18a535a043686..628a05d3f57ce 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -38,6 +38,15 @@ gpio-restart { }; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; + }; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index d71f11a10b3d2..fb0bc3b241204 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -51,6 +51,15 @@ i2cmux_s32: i2cmux-3 { }; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl";