From patchwork Wed Jul 8 17:50:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11652071 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B110513BD for ; Wed, 8 Jul 2020 17:50:57 +0000 (UTC) Received: by mail.kernel.org (Postfix) id AB813206F6; Wed, 8 Jul 2020 17:50:57 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D1C5206E9; Wed, 8 Jul 2020 17:50:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7D1C5206E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: E900WULXyg0ynfOfikzhxEnu5nFf1Y87PksYTPlYyVpvNH/MZgHMSNU8VNLQ78eVTPVLYnm9Sh pN3++VH4n3iw== X-IronPort-AV: E=McAfee;i="6000,8403,9676"; a="209405844" X-IronPort-AV: E=Sophos;i="5.75,328,1589266800"; d="scan'208";a="209405844" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 10:50:57 -0700 IronPort-SDR: hQqu/5M6q4nS/e14LAVyoT9Jl2/HL/XMHI5+al7gkntaeU8cIWSarqjxPsXnj+BSFkjrLKHFf5 ZfxZ72M8rZjA== X-IronPort-AV: E=Sophos;i="5.75,328,1589266800"; d="scan'208";a="457591975" Received: from sgyanama-mobl1.gar.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.252.5.67]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 10:50:53 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Jassi Brar , Arnd Bergmann , Olof Johansson Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Dinh Nguyen , Paul Murphy , Will Deacon , Daniele Alessandrelli Subject: [PATCH v2 4/5] arm64: dts: keembay: Add device tree for Keem Bay SoC Date: Wed, 8 Jul 2020 18:50:19 +0100 Message-Id: <20200708175020.194436-5-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200708175020.194436-1-daniele.alessandrelli@linux.intel.com> References: <20200708175020.194436-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add initial device tree for Intel Movidius SoC code-named Keem Bay. This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI, and PMU. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/keembay-soc.dtsi | 125 +++++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index ceb833fa04dd..53d2f8d0976a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-soc.dtsi F: include/dt-bindings/clock/keembay-clocks.h F: include/dt-bindings/power/keembay-power.h diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi new file mode 100644 index 000000000000..4aaf543f3ad1 --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020, Intel Corporation. + * + * Device tree describing Keem Bay SoC. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@20500000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ + <0x0 0x20580000 0x0 0x80000>; /* GICR */ + /* VGIC maintenance interrupt */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Secure, non-secure, virtual, and hypervisor */ + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@20150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20150000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@20160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20160000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20170000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@20180000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20180000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +};