From patchwork Fri Jul 17 09:04:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Alessandrelli X-Patchwork-Id: 11669593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB66114E3 for ; Fri, 17 Jul 2020 09:04:53 +0000 (UTC) Received: by mail.kernel.org (Postfix) id B439D207FB; Fri, 17 Jul 2020 09:04:53 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 77132208C7; Fri, 17 Jul 2020 09:04:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 77132208C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=daniele.alessandrelli@linux.intel.com IronPort-SDR: TmrtbYGdxv6cqPuFEMvbDPVvHhFHE8ghaFyOx+8XbuT2RfMhiQmJh5pUQDoRqwZpcB1CrJjani Pxe0wDdlo3rA== X-IronPort-AV: E=McAfee;i="6000,8403,9684"; a="129643989" X-IronPort-AV: E=Sophos;i="5.75,362,1589266800"; d="scan'208";a="129643989" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2020 02:04:53 -0700 IronPort-SDR: YgJHoyvkGLm8E3XMELd+y0kTlaFb+I9OU8g+ckzZ+p/Iw7UvfjRAROwPtOfyWm3bWivUcjQWbE fvVxOeacPVOQ== X-IronPort-AV: E=Sophos;i="5.75,362,1589266800"; d="scan'208";a="460786150" Received: from enaessen-mobl1.ger.corp.intel.com (HELO dalessan-mobl1.ir.intel.com) ([10.251.86.9]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2020 02:04:49 -0700 From: Daniele Alessandrelli List-Id: To: linux-arm-kernel@lists.infradead.org, SoC Team , Rob Herring , Arnd Bergmann , Olof Johansson Cc: Daniele Alessandrelli , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Catalin Marinas , Will Deacon , "Paul J. Murphy" , "Paul J. Murphy" , Dinh Nguyen Subject: [PATCH v4 4/5] arm64: dts: keembay: Add device tree for Keem Bay SoC Date: Fri, 17 Jul 2020 10:04:13 +0100 Message-Id: <20200717090414.313530-5-daniele.alessandrelli@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717090414.313530-1-daniele.alessandrelli@linux.intel.com> References: <20200717090414.313530-1-daniele.alessandrelli@linux.intel.com> MIME-Version: 1.0 From: Daniele Alessandrelli Add initial device tree for Intel Movidius SoC code-named Keem Bay. This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI, and PMU. Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/keembay-soc.dtsi | 123 +++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 3babb333b556..82ca9748fb70 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/intel,keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-soc.dtsi ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT M: Jonathan Cameron diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi new file mode 100644 index 000000000000..781761d2942b --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation. + * + * Device tree describing Keem Bay SoC. + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@20500000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ + <0x0 0x20580000 0x0 0x80000>; /* GICR */ + /* VGIC maintenance interrupt */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Secure, non-secure, virtual, and hypervisor */ + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@20150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20150000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@20160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20160000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20170000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@20180000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20180000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +};