From patchwork Fri Jul 24 13:26:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hawa, Hanna" X-Patchwork-Id: 11683263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41496618 for ; Fri, 24 Jul 2020 13:28:30 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 3B39520768; Fri, 24 Jul 2020 13:28:30 +0000 (UTC) Delivered-To: soc@kernel.org Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A42792065F; Fri, 24 Jul 2020 13:28:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b="JW/Qkg96" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A42792065F Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=prvs=467992d33=hhhawa@amazon.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1595597310; x=1627133310; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ndZnobQDkKrkO7PlwHAI/yOaDjmUOeSNHsflymP+n4c=; b=JW/Qkg96eejBO5tc/nxWUHsQBp+7AaChbB+zMgQh7JGPwHmiYWnOnywT N1nE0X5oyzJq2ebfqdHnv/ZWzRhOJ0UtEwqz2ZYVrSbQpEzrcRCIo9DKf 1+vbx4bAqP15M3pIW0AbkzXNvqN6Yvsxp526woW0w6WEXIZbHvJ5h/udF Y=; IronPort-SDR: vxShPv83CaRSi0i0poBSsdf+mwE2lVrsSmdrd7Re08ZWIhHds7aoqLaSxfJ4TbdIENXPMQnFEc f0xMji0QwPrA== X-IronPort-AV: E=Sophos;i="5.75,390,1589241600"; d="scan'208";a="43769498" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2c-1968f9fa.us-west-2.amazon.com) ([10.43.8.6]) by smtp-border-fw-out-6002.iad6.amazon.com with ESMTP; 24 Jul 2020 13:28:28 +0000 Received: from EX13MTAUEA002.ant.amazon.com (pdx4-ws-svc-p6-lb7-vlan3.pdx.amazon.com [10.170.41.166]) by email-inbound-relay-2c-1968f9fa.us-west-2.amazon.com (Postfix) with ESMTPS id 52C18A27D2; Fri, 24 Jul 2020 13:28:27 +0000 (UTC) Received: from EX13D19EUB001.ant.amazon.com (10.43.166.229) by EX13MTAUEA002.ant.amazon.com (10.43.61.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 24 Jul 2020 13:28:26 +0000 Received: from u8a88181e7b2355.ant.amazon.com (10.43.160.65) by EX13D19EUB001.ant.amazon.com (10.43.166.229) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 24 Jul 2020 13:28:18 +0000 From: Hanna Hawa To: , , , , , List-Id: CC: , , , , , , , , , , , , Subject: [PATCH v6 6/6] arm64: dts: amazon: add Amazon's Annapurna Labs Alpine v3 support Date: Fri, 24 Jul 2020 16:26:54 +0300 Message-ID: <20200724132654.16549-7-hhhawa@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200724132654.16549-1-hhhawa@amazon.com> References: <20200724132654.16549-1-hhhawa@amazon.com> MIME-Version: 1.0 X-Originating-IP: [10.43.160.65] X-ClientProxiedBy: EX13D32UWA004.ant.amazon.com (10.43.160.193) To EX13D19EUB001.ant.amazon.com (10.43.166.229) From: Ronen Krupnik This patch adds the initial support for the Amazon's Annapurna Labs Alpine v3 Soc and Evaluation Platform (EVP). Signed-off-by: Ronen Krupnik Signed-off-by: Talel Shenhar Signed-off-by: Hanna Hawa Acked-by: Antoine Tenart --- arch/arm64/boot/dts/amazon/Makefile | 1 + arch/arm64/boot/dts/amazon/alpine-v3-evp.dts | 24 ++ arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 408 +++++++++++++++++++ 3 files changed, 433 insertions(+) create mode 100644 arch/arm64/boot/dts/amazon/alpine-v3-evp.dts create mode 100644 arch/arm64/boot/dts/amazon/alpine-v3.dtsi diff --git a/arch/arm64/boot/dts/amazon/Makefile b/arch/arm64/boot/dts/amazon/Makefile index d79822dc30cd..ba9e11544905 100644 --- a/arch/arm64/boot/dts/amazon/Makefile +++ b/arch/arm64/boot/dts/amazon/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb +dtb-$(CONFIG_ARCH_ALPINE) += alpine-v3-evp.dtb diff --git a/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts b/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts new file mode 100644 index 000000000000..48078f5ea545 --- /dev/null +++ b/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + */ + +#include "alpine-v3.dtsi" + +/ { + model = "Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP)"; + compatible = "amazon,al-alpine-v3-evp", "amazon,al-alpine-v3"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi new file mode 100644 index 000000000000..73a352ea8fd5 --- /dev/null +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved + */ + +/dts-v1/; + +#include + +/ { + model = "Amazon's Annapurna Labs Alpine v3"; + compatible = "amazon,al-alpine-v3"; + + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster0_l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster0_l2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x2>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster0_l2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x3>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster0_l2>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x100>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster1_l2>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x101>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster1_l2>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x102>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster1_l2>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x103>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster1_l2>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x200>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster2_l2>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x201>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster2_l2>; + }; + + cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x202>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster2_l2>; + }; + + cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x203>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster2_l2>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x300>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster3_l2>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x301>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster3_l2>; + }; + + cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x302>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster3_l2>; + }; + + cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x303>; + enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: cache@0 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-level = <2>; + }; + + cluster1_l2: cache@100 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-level = <2>; + }; + + cluster2_l2: cache@200 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-level = <2>; + }; + + cluster3_l2: cache@300 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-level = <2>; + }; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secmon@0 { + reg = <0x0 0x0 0x0 0x100000>; + no-map; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f0000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xf0800000 0 0x10000>, /* GICD */ + <0x0 0xf0a00000 0 0x200000>, /* GICR */ + <0x0 0xf0000000 0 0x2000>, /* GICC */ + <0x0 0xf0010000 0 0x1000>, /* GICH */ + <0x0 0xf0020000 0 0x2000>; /* GICV */ + interrupts = ; + }; + + pcie@fbd00000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #size-cells = <2>; + #address-cells = <3>; + #interrupt-cells = <1>; + reg = <0x0 0xfbd00000 0x0 0x100000>; + interrupt-map-mask = <0xf800 0 0 7>; + /* 8 x legacy interrupts for SATA only */ + interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, + <0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>, + <0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>, + <0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>, + <0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>, + <0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>, + <0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>, + <0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; + bus-range = <0x00 0x00>; + msi-parent = <&msix>; + }; + + msix: msix@fbe00000 { + compatible = "al,alpine-msix"; + reg = <0x0 0xfbe00000 0x0 0x100000>; + interrupt-controller; + msi-controller; + al,msi-base-spi = <336>; + al,msi-num-spis = <959>; + interrupt-parent = <&gic>; + }; + + io-fabric { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xfc000000 0x2000000>; + + uart0: serial@1883000 { + compatible = "ns16550a"; + reg = <0x1883000 0x1000>; + interrupts = ; + clock-frequency = <0>; /* Filled by firmware */ + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@1884000 { + compatible = "ns16550a"; + reg = <0x1884000 0x1000>; + interrupts = ; + clock-frequency = <0>; /* Filled by firmware */ + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@1885000 { + compatible = "ns16550a"; + reg = <0x1885000 0x1000>; + interrupts = ; + clock-frequency = <0>; /* Filled by firmware */ + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@1886000 { + compatible = "ns16550a"; + reg = <0x1886000 0x1000>; + interrupts = ; + clock-frequency = <0>; /* Filled by firmware */ + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; + }; +};