From patchwork Tue Jul 28 10:03:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11688809 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 793AD6C1 for ; Tue, 28 Jul 2020 10:03:57 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 74B8920792; Tue, 28 Jul 2020 10:03:57 +0000 (UTC) Delivered-To: soc@kernel.org Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5374620829 for ; Tue, 28 Jul 2020 10:03:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="Wv+dkdLg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5374620829 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pl1-f195.google.com with SMTP id m16so9624635pls.5 for ; Tue, 28 Jul 2020 03:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TqL6Hf6c4QekoFaLOlZu1oX0uTrAmJv+cvAaJuBUQvY=; b=Wv+dkdLgt5GaTHUTC/zxSY0/FqradzfyAopvOn1bQ1JvKPgFGgUAds2ZLqfsUngRTK 1MXSX/omDXR6Qeo+mkRGjd3WqRMSDLnwV+r3o/s07aaiTR4sln2PkDtwTYPf3QolzgHS 2wb2lh8g3wPmHx57IMN/erWNWw8kt73tMJOvw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TqL6Hf6c4QekoFaLOlZu1oX0uTrAmJv+cvAaJuBUQvY=; b=CjgyFLiuwquwBWPC9z1DRCGOg2oxCUKZ8/E7HAqFQcUF6TmUlo/kGa75kF2dFyLmaf OfheDRfl7iYf/9qVbgwIPPww+o9y8Y5wCdT+StG34UWl/uav81tI1bEFoQeoL8R1Lmd2 vltDs2urbZprQG4DOQAWm4/EiXlJ2XoJjJ1rXEsmC7MawkI2WLjWMHSBVCAaHkyMuoFA lWVucKzrfQpN+x9vDfbq6cuTB6LbDM0yK11kXtLZLyBCx6S3p0sfhIxgqflJb8OT3QST ns31ng2uQz9/Gub/WWXAnkr8toAWCY2L+4N03sbRXpmZ1Y1sQ3ahaxkVwF823UtAzsJD d3rQ== X-Gm-Message-State: AOAM532GII4MevJSs2D82a3i9dtjUqYNSNCvNXGB9EfCxIVgo5LznLxc xne4kUu5noRF2kRXcOhuP4WBp+ZT9HM= X-Google-Smtp-Source: ABdhPJwIMReWpM39kk9lbKtgYuSrVGQ0fXaPXcyqtWpE61ZnhacKeju0jsGrkiCHXZ05muiy3/Sn4A== X-Received: by 2002:a17:90b:f16:: with SMTP id br22mr3914793pjb.170.1595930636601; Tue, 28 Jul 2020 03:03:56 -0700 (PDT) Received: from shiro.work (p532183-ipngn200506sizuokaden.shizuoka.ocn.ne.jp. [153.199.2.183]) by smtp.googlemail.com with ESMTPSA id u66sm17779018pfb.191.2020.07.28.03.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 03:03:56 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, arnd@arndb.de, robh@kernel.org, Daniel Palmer Subject: [PATCH v2 9/9] ARM: mstar: Add reboot support Date: Tue, 28 Jul 2020 19:03:21 +0900 Message-Id: <20200728100321.1691745-10-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728100321.1691745-1-daniel@0x0f.com> References: <20200728100321.1691745-1-daniel@0x0f.com> MIME-Version: 1.0 MStar v7 SoCs support reset by writing a magic value to a register in the "pmsleep" area. This adds a node for using the syscon reboot driver to trigger a reset. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index bb7fb3e689a7..c7458c67c4df 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -78,6 +78,13 @@ pmsleep: syscon@1c00 { reg = <0x1c00 0x100>; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&pmsleep>; + offset = <0xb8>; + mask = <0x79>; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>;