From patchwork Mon Aug 24 15:10:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11733375 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04F28138A for ; Mon, 24 Aug 2020 15:10:54 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 00DD1206F0; Mon, 24 Aug 2020 15:10:54 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF6FE206B5; Mon, 24 Aug 2020 15:10:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MFiALiEI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF6FE206B5 Authentication-Results: mail.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1598281853; x=1629817853; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Olbw4+eagxlIiCMHRbBmMPr4NjxHK3uFqmkVqHcK/q4=; b=MFiALiEIcMPgLGqb71oVI6vuXBT2/pJknUeK03uJSriP1n4g3M8H586z ImGGeA2ZdUx7+bN0mOjPo+d/KxnB7KY83Obd2VuG09SuPog+MXKnrjtBw PSq3am3QvO3bxHWTfeJ8SelwJt1FxJLQKILQOAP5vH6qcqWQbNAdpP2pW jF4IyYZbleC1xK4Xl48L8bTQPpZpxioI67225phtFxPijDpHdMLWpVsP6 ujo7/QtUsqyfxInMyrzUqJRi4DTspcWSTqsBBjDa3TvPbfk10Z8dNrGTC qHVgkWsLJnbPX+d5xIGSQrGB8iH8er2jDz2Ocxp9Uwf6sDed8Dpblq8YH A==; IronPort-SDR: l6xZfwp0+YCYmNFBUJ610+1789b35PQU9MMYkn1FPg3R0jHyLbiabiAqItRsG6hOuLhkQBaScu qZ5d/iawBKWsi+4qRfBntul44U/DGn6UUip/nwgyyn1YUFgXVV5ylb6eBmXFCDyz+21+Wty96L azJ+7TUBu5oZ8caO79DN2A79Hy3BqIPv4b+UHeBBAWbdklstKcPhEQeY6gpb5S25hEupWNjeXu vv0yyh8oKFDrjQh+Jv5xNcGAEfsAFxJPncs2TdONMAAzmJS3Jx10oYFo75TbLJiE4NKsazMfg1 a7c= X-IronPort-AV: E=Sophos;i="5.76,349,1592895600"; d="scan'208";a="86699606" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2020 08:10:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 24 Aug 2020 08:10:49 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Mon, 24 Aug 2020 08:10:46 -0700 From: Lars Povlsen List-Id: To: Ulf Hansson , Adrian Hunter , SoC Team , Rob Herring CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Date: Mon, 24 Aug 2020 17:10:33 +0200 Message-ID: <20200824151035.31093-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200824151035.31093-1-lars.povlsen@microchip.com> References: <20200824151035.31093-1-lars.povlsen@microchip.com> MIME-Version: 1.0 The Sparx5 SDHCI controller is based on the Designware controller IP. Signed-off-by: Lars Povlsen --- .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml -- 2.27.0 diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml new file mode 100644 index 0000000000000..55883290543b9 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Mobile Storage Host Controller Binding + +allOf: + - $ref: "mmc-controller.yaml" + +maintainers: + - Lars Povlsen + +# Everything else is described in the common file +properties: + compatible: + const: microchip,dw-sparx5-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Handle to "core" clock for the sdhci controller. + + clock-names: + items: + - const: core + + microchip,clock-delay: + description: Delay clock to card to meet setup time requirements. + Each step increase by 1.25ns. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1 + maximum: 15 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + #include + sdhci0: mmc@600800000 { + compatible = "microchip,dw-sparx5-sdhci"; + reg = <0x00800000 0x1000>; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + clocks = <&clks CLK_ID_AUX1>; + clock-names = "core"; + assigned-clocks = <&clks CLK_ID_AUX1>; + assigned-clock-rates = <800000000>; + interrupts = ; + bus-width = <8>; + microchip,clock-delay = <10>; + };