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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:31 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 8/8] ARM: mstar: Add OPP table for mercury5 Date: Tue, 23 Feb 2021 15:18:30 +0900 Message-Id: <20210223061830.1913700-9-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011934_254354_00D6330F X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an OPP table for mercury5 so that cpu frequency scaling can happen. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi index a7d0dd9d6132..80a19bd23c9c 100644 --- a/arch/arm/boot/dts/mstar-mercury5.dtsi +++ b/arch/arm/boot/dts/mstar-mercury5.dtsi @@ -6,6 +6,42 @@ #include "mstar-v7.dtsi" +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000 800000 850000>; + clock-latency-ns = <300000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <850000 850000 880000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <880000 880000 890000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000 900000 1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + &imi { reg = <0xa0000000 0x20000>; };