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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id p12sm5278968pjo.4.2021.04.22.07.09.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 07:09:59 -0700 (PDT) From: Daniel Palmer List-Id: To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: olof@lixom.net, arnd@kernel.org, w@1wt.eu, Daniel Palmer Subject: [RFC PATCH 1/2] ARM: mstar: Add header with macros for RIU register access Date: Thu, 22 Apr 2021 23:09:44 +0900 Message-Id: <20210422140945.4131092-2-daniel@0x0f.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210422140945.4131092-1-daniel@0x0f.com> References: <20210422140945.4131092-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210422_071000_737277_CE5E2C29 X-CRM114-Status: GOOD ( 20.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Registers connected to the CPU via "RIU" (Maybe Register Interface Unit) are 16bits wide with a 32bit stride. For IPs that came from 3rd parties that have natively 32bit registers they are annoyingly mapped with the 32bit register split into two 16bit registers. This means that any existing driver (i.e. the usb and ethernet) cannot be used as is and needs to use a special readl()/writel() to fix up the address of the register that needs to be accessed, do two readw()/writel()s and stitch the values together. To avoid having this code in every driver add a header with an implementation of readl()/writel() that patches over the insanity. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + include/soc/mstar/riu.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/soc/mstar/riu.h diff --git a/MAINTAINERS b/MAINTAINERS index 19dc2eb0d93b..9600291e73a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2155,6 +2155,7 @@ F: drivers/gpio/gpio-msc313.c F: drivers/pinctrl/pinctrl-msc313.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h +F: include/soc/mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky diff --git a/include/soc/mstar/riu.h b/include/soc/mstar/riu.h new file mode 100644 index 000000000000..5aeea9c1e7eb --- /dev/null +++ b/include/soc/mstar/riu.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _SOC_MSTAR_RIU_H_ +#define _SOC_MSTAR_RIU_H_ + +#include + +static inline u32 riu_readl(__iomem void *base, unsigned int offset) +{ + __iomem void *reg = base + (offset * 2); + + return readw_relaxed(reg + 4) << 16 | readw_relaxed(reg); +} + +static inline void riu_writel(__iomem void *base, unsigned int offset, u32 value) +{ + __iomem void *reg = base + (offset * 2); + + /* + * Do not change this order. For EMAC at least + * the write order must be the lower half and then + * the upper half otherwise it doesn't work. + */ + writew_relaxed(value, reg); + writew_relaxed(value >> 16, reg + 4); +} + +#endif