From patchwork Fri Jun 25 09:49:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Hagan X-Patchwork-Id: 12344673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6414DC2B9F4 for ; Fri, 25 Jun 2021 09:50:44 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 4B89E6142C; Fri, 25 Jun 2021 09:50:44 +0000 (UTC) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1790961423; Fri, 25 Jun 2021 09:50:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1790961423 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=mnhagan88@gmail.com Received: by mail-wr1-f44.google.com with SMTP id i94so9926372wri.4; Fri, 25 Jun 2021 02:50:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HZO5u/6pDWKzzSomryd0rz22fToGF/wQIJsnLa3t0o4=; b=axXF/PYmPO0Ih8yvRD8gnf4EH3KvVxaWhS0CSOtHcoonNpwwz63DFzBA+hGCMszgFB lKg3t7kTTauE+V73SYhguwZhAOD/YMOU2KBoSv0ZSA4Ia5iMChDENPjM0ILh9/vOWo0n OKOy/2Md+DM5SYQ2RI6EF5CPa70NcweR05f5N5DT4cHwpfyNQtRI0AFOH5Md+MaHIW6s gHrWVZ/0zhFlRmDtJzp2Jk65nXm2hMV8vBjypas70gmAm97I1VJBF5mXqtI/Sx7BiMlr +oHkUXmM+0jJiQzFpSLO2MDoCLEtlvQOOiR8Zkfda2iSdC5bRbMI4lhRXm4qnL98s+YS AWfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HZO5u/6pDWKzzSomryd0rz22fToGF/wQIJsnLa3t0o4=; b=JFfCGQ57zkdMtaHBPkpjWWy2iFGBePwKFKcC0mkA744xmzsWDxbY2V1pE3w9BDxBZw upUwiuEt7QVGIBlB4+bPeTFKk4b426Pl6fqJe1OeBOzGAljZWM9gFLvI1kN/1ugajYNj F/2vNX86xtIsLyw7kTAcP6NdS/zz0mwkNStEcMtWfsI9ers4kIQHXMIijaVFMfKovTsJ OxY9yEOEEMWXojW7VQwJNlFAF62XN2XwGGnkzVSS2C7dGhr8P1BxDnYIcwIBJ6VyzfeS wi1t+A+Ev92vwEnxfkKVHlrrPXvSHf1u68dyWZ8pSt0LhDTfjdgo18Rl5NdKJzPkiCDB S4vA== X-Gm-Message-State: AOAM531C2DUhsRiu9DSFGuCaSprVZNdVHRmfQA0lTFMhf6IFBWlVK6Ac +5ZyrPgETK4nkIwBd6ewnYY= X-Google-Smtp-Source: ABdhPJy7HuVDArt+9+sYwvEik2CMbd5g4Tak4Me88lVTzYEusyxW7pHVkoPRkskmOQPMpq1Tw5waUg== X-Received: by 2002:adf:f30d:: with SMTP id i13mr9821882wro.119.1624614642772; Fri, 25 Jun 2021 02:50:42 -0700 (PDT) Received: from cluster5 ([80.76.206.81]) by smtp.gmail.com with ESMTPSA id 2sm5432075wrz.87.2021.06.25.02.50.42 (version=TLS1 cipher=ECDHE-ECDSA-AES128-SHA bits=128/128); Fri, 25 Jun 2021 02:50:42 -0700 (PDT) From: Matthew Hagan To: List-Id: Cc: Florian Fainelli , Vladimir Oltean , Matthew Hagan , Rob Herring , Arnd Bergmann , Olof Johansson , soc@kernel.org, Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Viresh Kumar , Sam Ravnborg , Geert Uytterhoeven , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/4] ARM: dts: NSP: Add DT files for Meraki MX64 series Date: Fri, 25 Jun 2021 10:49:49 +0100 Message-Id: <20210625095000.3358973-3-mnhagan88@gmail.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210625095000.3358973-1-mnhagan88@gmail.com> References: <20210625095000.3358973-1-mnhagan88@gmail.com> MIME-Version: 1.0 MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan --- arch/arm/boot/dts/Makefile | 4 + .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 45 +++++ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 15 ++ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 55 ++++++ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 23 +++ 6 files changed, 305 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e7..83560b05f797 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -154,6 +154,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958525xmc.dtb \ bcm958622hr.dtb \ bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi new file mode 100644 index 000000000000..7c487c74fd10 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +#include "bcm958625-meraki-mx6x-common.dtsi" + +/ { + + keys { + compatible = "gpio-keys-polled"; + autorepeat; + poll-interval = <20>; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* green:lan1-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <0>; + color = ; + gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* green:lan1-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <1>; + color = ; + gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* green:lan2-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <2>; + color = ; + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* green:lan2-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <3>; + color = ; + gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* green:lan3-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <4>; + color = ; + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* green:lan3-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <5>; + color = ; + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; + }; + + led-6 { + /* green:lan4-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <6>; + color = ; + gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; + }; + + led-7 { + /* green:lan4-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <7>; + color = ; + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; + }; + + led-8 { + /* green:wan-left */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <8>; + color = ; + gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; + }; + + led-9 { + /* green:wan-right */ + function = LED_FUNCTION_ACTIVITY; + function-enumerator = <9>; + color = ; + gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; + }; + + led-a { + /* amber:power */ + function = LED_FUNCTION_POWER; + color = ; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-b { + /* white:status */ + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan1"; + reg = <0>; + }; + + port@1 { + label = "lan2"; + reg = <1>; + }; + + port@2 { + label = "lan3"; + reg = <2>; + }; + + port@3 { + label = "lan4"; + reg = <3>; + }; + + port@4 { + label = "wan"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts new file mode 100644 index 000000000000..f9c8180293ed --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64(A0)"; + compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&L2 { + /delete-property/ arm,io-coherent; + /delete-property/ prefetch-data; + /delete-property/ prefetch-instr; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts new file mode 100644 index 000000000000..58addd69688a --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64"; + compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts new file mode 100644 index 000000000000..807720d21660 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W(A0)"; + compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; +}; + +&amac2 { + /delete-property/ dma-coherent; +}; + +&cpu1 { + secondary-boot-reg = <0xffff042c>; +}; + +&ehci0 { + /delete-property/ dma-coherent; +}; + +&i2c0 { + /delete-property/ dma-coherent; +}; + +&L2 { + /delete-property/ arm,io-coherent; + /delete-property/ prefetch-data; + /delete-property/ prefetch-instr; +}; + +&mailbox { + /delete-property/ dma-coherent; +}; + +&ohci0 { + /delete-property/ dma-coherent; +}; + +&pcie0 { + /delete-property/ dma-coherent; + status = "okay"; +}; + +&pcie1 { + /delete-property/ dma-coherent; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts new file mode 100644 index 000000000000..8d37cd56c093 --- /dev/null +++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. + * + * Copyright (C) 2020-2021 Matthew Hagan + */ + +/dts-v1/; + +#include "bcm958625-meraki-kingpin.dtsi" + +/ { + model = "Cisco Meraki MX64W"; + compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +};