| Message ID | 20211021090955.115005-1-krzysztof.kozlowski@canonical.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [GIT,PULL] riscv: dts: few cleanups for v5.16 | expand |
On Thu, Oct 21, 2021 at 11:09 AM Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> wrote: > > Hi Arnd and Olof, > > I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in > August 2021 (v1, v2), resent in September and pinged two times. They got some > review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but > unfortunately Palmer (RISC-V maintainer) did not respond here. > > The usual RISC-V patches go via Palmer to Linus and I am not planning to change > that, but I want to get these fixed. > > Could you grab these to soc tree? Sure, I can add them to a separate branch in the soc tree, in case the riscv maintainers take them after all. I notice that you have only Cc'd Palmer, but not the other two maintainers or the RISC-V mainling list. Adding them here to maybe get their attention. Arnd
On 21/10/2021 14:23, Arnd Bergmann wrote: > On Thu, Oct 21, 2021 at 11:09 AM Krzysztof Kozlowski > <krzysztof.kozlowski@canonical.com> wrote: >> >> Hi Arnd and Olof, >> >> I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in >> August 2021 (v1, v2), resent in September and pinged two times. They got some >> review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but >> unfortunately Palmer (RISC-V maintainer) did not respond here. >> >> The usual RISC-V patches go via Palmer to Linus and I am not planning to change >> that, but I want to get these fixed. >> >> Could you grab these to soc tree? > > Sure, I can add them to a separate branch in the soc tree, in case the > riscv maintainers > take them after all. I notice that you have only Cc'd Palmer, but not > the other two > maintainers or the RISC-V mainling list. Adding them here to maybe get their > attention. Yes, my bad. Thanks for cc-ing them. Best regards, Krzysztof
On 21/10/2021 13:23, Arnd Bergmann wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Thu, Oct 21, 2021 at 11:09 AM Krzysztof Kozlowski > <krzysztof.kozlowski@canonical.com> wrote: >> Hi Arnd and Olof, >> >> I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in >> August 2021 (v1, v2), resent in September and pinged two times. They got some >> review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but >> unfortunately Palmer (RISC-V maintainer) did not respond here. Out of curiosity which series is this one? Is it the one with the plic/clint changes? Pretty sure that I have taken them in internally, but I am going to submit a bunch of changes to our device tree soon (tm) and want to make sure I have the right dependent series listed. >> >> The usual RISC-V patches go via Palmer to Linus and I am not planning to change >> that, but I want to get these fixed. >> >> Could you grab these to soc tree? > Sure, I can add them to a separate branch in the soc tree, in case the > riscv maintainers > take them after all. I notice that you have only Cc'd Palmer, but not > the other two > maintainers or the RISC-V mainling list. Adding them here to maybe get their > attention. > > Arnd > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 21/10/2021 15:06, Conor.Dooley@microchip.com wrote: > On 21/10/2021 13:23, Arnd Bergmann wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On Thu, Oct 21, 2021 at 11:09 AM Krzysztof Kozlowski >> <krzysztof.kozlowski@canonical.com> wrote: >>> Hi Arnd and Olof, >>> >>> I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in >>> August 2021 (v1, v2), resent in September and pinged two times. They got some >>> review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but >>> unfortunately Palmer (RISC-V maintainer) did not respond here. > > Out of curiosity which series is this one? Is it the one with the > plic/clint changes? > Pretty sure that I have taken them in internally, but I am going to > submit a bunch > of changes to our device tree soon (tm) and want to make sure I have the > right > dependent series listed. > There is only one Microchip patch here (plic/clint). Others are for SiFive. All the patches are described in the pull reqeust: https://lore.kernel.org/lkml/20211021090955.115005-1-krzysztof.kozlowski@canonical.com/ I had also second set of RISC-V patches for Microchip. These were picked up by Palmer: https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next Best regards, Krzysztof
On Thu, 21 Oct 2021 06:09:50 PDT (-0700), krzysztof.kozlowski@canonical.com wrote: > On 21/10/2021 15:06, Conor.Dooley@microchip.com wrote: >> On 21/10/2021 13:23, Arnd Bergmann wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> On Thu, Oct 21, 2021 at 11:09 AM Krzysztof Kozlowski >>> <krzysztof.kozlowski@canonical.com> wrote: >>>> Hi Arnd and Olof, >>>> >>>> I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in >>>> August 2021 (v1, v2), resent in September and pinged two times. They got some >>>> review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but >>>> unfortunately Palmer (RISC-V maintainer) did not respond here. >> >> Out of curiosity which series is this one? Is it the one with the >> plic/clint changes? >> Pretty sure that I have taken them in internally, but I am going to >> submit a bunch >> of changes to our device tree soon (tm) and want to make sure I have the >> right >> dependent series listed. >> > > There is only one Microchip patch here (plic/clint). Others are for > SiFive. All the patches are described in the pull reqeust: > https://lore.kernel.org/lkml/20211021090955.115005-1-krzysztof.kozlowski@canonical.com/ > > I had also second set of RISC-V patches for Microchip. These were picked > up by Palmer: > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next Sorry I missed this. If you guys took this through the SOC tree that's fine, otherwise LMK and I'll put it in the RISC-V tree.
On Thu, Oct 21, 2021 at 5:06 PM Palmer Dabbelt <palmerdabbelt@google.com> wrote: > On Thu, 21 Oct 2021 06:09:50 PDT (-0700), krzysztof.kozlowski@canonical.com wrote: > > > > There is only one Microchip patch here (plic/clint). Others are for > > SiFive. All the patches are described in the pull reqeust: > > https://lore.kernel.org/lkml/20211021090955.115005-1-krzysztof.kozlowski@canonical.com/ > > > > I had also second set of RISC-V patches for Microchip. These were picked > > up by Palmer: > > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next > > Sorry I missed this. If you guys took this through the SOC tree that's > fine, otherwise LMK and I'll put it in the RISC-V tree. I haven't merged it yet, please add it to your tree then. Arnd
On Thu, 21 Oct 2021 08:18:16 PDT (-0700), Arnd Bergmann wrote: > On Thu, Oct 21, 2021 at 5:06 PM Palmer Dabbelt <palmerdabbelt@google.com> wrote: >> On Thu, 21 Oct 2021 06:09:50 PDT (-0700), krzysztof.kozlowski@canonical.com wrote: >> > >> > There is only one Microchip patch here (plic/clint). Others are for >> > SiFive. All the patches are described in the pull reqeust: >> > https://lore.kernel.org/lkml/20211021090955.115005-1-krzysztof.kozlowski@canonical.com/ >> > >> > I had also second set of RISC-V patches for Microchip. These were picked >> > up by Palmer: >> > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next >> >> Sorry I missed this. If you guys took this through the SOC tree that's >> fine, otherwise LMK and I'll put it in the RISC-V tree. > > I haven't merged it yet, please add it to your tree then. OK, it's in. Sorry for missing this, IRC is always a good bet for these sorts of things as my inbox can get pretty hosed.
On 21/10/2021 17:35, Palmer Dabbelt wrote: > On Thu, 21 Oct 2021 08:18:16 PDT (-0700), Arnd Bergmann wrote: >> On Thu, Oct 21, 2021 at 5:06 PM Palmer Dabbelt <palmerdabbelt@google.com> wrote: >>> On Thu, 21 Oct 2021 06:09:50 PDT (-0700), krzysztof.kozlowski@canonical.com wrote: >>>> >>>> There is only one Microchip patch here (plic/clint). Others are for >>>> SiFive. All the patches are described in the pull reqeust: >>>> https://lore.kernel.org/lkml/20211021090955.115005-1-krzysztof.kozlowski@canonical.com/ >>>> >>>> I had also second set of RISC-V patches for Microchip. These were picked >>>> up by Palmer: >>>> https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next >>> >>> Sorry I missed this. If you guys took this through the SOC tree that's >>> fine, otherwise LMK and I'll put it in the RISC-V tree. >> >> I haven't merged it yet, please add it to your tree then. > > OK, it's in. Sorry for missing this, IRC is always a good bet for these > sorts of things as my inbox can get pretty hosed. Great, thanks! Best regards, Krzysztof
Hi Arnd and Olof, I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in August 2021 (v1, v2), resent in September and pinged two times. They got some review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but unfortunately Palmer (RISC-V maintainer) did not respond here. The usual RISC-V patches go via Palmer to Linus and I am not planning to change that, but I want to get these fixed. Could you grab these to soc tree? Best regards, Krzysztof The following changes since commit 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f: Linux 5.15-rc1 (2021-09-12 16:28:37 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/riscv-sifive-dt-5.16 for you to fetch changes up to 9962a066f3c1d4588d0dd876ceac2c03ef87acf3: riscv: dts: sifive: add missing compatible for plic (2021-10-19 10:59:57 +0200) ---------------------------------------------------------------- RISC-V DTS changes for v5.16 Cleanups of RISC-V SiFive and Microchip DTSes with dtschema. These are few minor fixes to make DTSes pass the dtschema, without actual functional effect. ---------------------------------------------------------------- Krzysztof Kozlowski (5): riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible riscv: dts: sifive: fix Unleashed board compatible riscv: dts: sifive: drop duplicated nodes and properties in sifive riscv: dts: microchip: add missing compatibles for clint and plic riscv: dts: sifive: add missing compatible for plic arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++-- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 10 +++------- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 7 +------ 4 files changed, 7 insertions(+), 16 deletions(-)