From patchwork Thu Mar 3 16:03:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12767708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C3E2C43219 for ; Thu, 3 Mar 2022 16:03:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 51318C004E1; Thu, 3 Mar 2022 16:03:48 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 6580EC340FC; Thu, 3 Mar 2022 16:03:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 6580EC340FC Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 86757223F0; Thu, 3 Mar 2022 17:03:39 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1646323419; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iFXEQ9bpa2qwjHSVEWYlqETOgXcSXZboSWvdCQL+/AI=; b=gL4tmEZ84cMEk5XZzI6PvZtwQfqDgJ4btJawjfsl5dzDDLMFb67ewDgxbMw84Pppn9voCs bQaCh0Sxrfb5FK2vOUaPw50iQkVkUpvsz9C2nOMF/gL4kMtbM+tYap/8qwr6/A71ZAXamD 06wIX9CklGtlV/ODFDoRKUWGvh8269U= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Michael Walle Subject: [PATCH v1 4/6] ARM: dts: lan966x: add flexcom SPI nodes Date: Thu, 3 Mar 2022 17:03:21 +0100 Message-Id: <20220303160323.3316317-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220303160323.3316317-1-michael@walle.cc> References: <20220303160323.3316317-1-michael@walle.cc> MIME-Version: 1.0 Add all the SPI nodes for the flexcom IP block. Keep them disabled by default. Signed-off-by: Michael Walle --- arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index bea69b6d2749..0616927f1bb1 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -105,6 +105,21 @@ usart0: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi0: spi@400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -128,6 +143,21 @@ usart1: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi1: spi@400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -168,6 +198,21 @@ usart2: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi2: spi@400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -191,6 +236,21 @@ usart3: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi3: spi@400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; dma0: dma-controller@e0068000 { @@ -233,6 +293,21 @@ usart4: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi4: spi@400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; timer0: timer@e008c000 {