From patchwork Sat Mar 26 14:43:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse T X-Patchwork-Id: 12792396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13211C433EF for ; Sat, 26 Mar 2022 14:43:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id F32A2C34100; Sat, 26 Mar 2022 14:43:52 +0000 (UTC) Received: from mail-qv1-f44.google.com (mail-qv1-f44.google.com [209.85.219.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id DE8C9C340EE; Sat, 26 Mar 2022 14:43:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org DE8C9C340EE Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-f44.google.com with SMTP id k7so8453837qvc.4; Sat, 26 Mar 2022 07:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vb2ZOaYsO4CyUWoU4mZse36oHT1LXfcvDTGWA9nha+g=; b=ZNlH3G7sic6bbMTQsp4SV8085iOZMqssE3HV43C50KJy33XbR5vidkI3FAmis6UR+b RagNkUet0iF2Y42wWL9ygEV6olNcAaDwTYyYGG/b1/dnEW89fgLrEMxsO0J/BMZLuAYW 37M5vOBiSewjXTBP6dFyLw201AGWDaHDWtRsZsmfOjO3gM6QY0NnXua2hOZ6P9kj9P9O JzBdO85/SyAtV1Ay9xW4t8Me20yeEFcIahbO+TVLURnveCpSGnzQweANm7gxt18Je8mP XZ8JXWQKQd3y0BGVPziFGMKEolcRjtoj8H44hTKydcp7oDbVv0W3C1g4sUa6+NbnrqCD /8bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vb2ZOaYsO4CyUWoU4mZse36oHT1LXfcvDTGWA9nha+g=; b=5Emtsa5WTPuQSwluKI8ucHnKzF484mErljgMIBCevCbtnEJMb+1tljgRjWDVw4QVZJ YO/xd123g5wjx6zREVQeT521Me/cLMJLgzHWxuzARLlfBxbn9xLr0kSmKAC3v8qeZzOc W1b13d21iTAMD+/MGPhs8SxqrEFCpCyziYAf5W6hgJ6R4kC3AadmTFq8SwyL6LbID/9f pQP7JPxp5XEOUh9id/XVJEGnvpVbxWNvLqoNuZKKwg9Gf5Phr5s046szWkoY0Iy2T6mQ mk9DKwF/7e+7bztKjX0khPJUPdVnAWthmv4k9knKrVKSJYsVa3HJQD/QjVuJ3K2udFZu CaSw== X-Gm-Message-State: AOAM532RjhYnPJ3wnxfSwVJAOHm/CCeO3AVXlfva+IhoJt7eu61x7o01 +qMjO8g0yzoGE9FEEy6w/gc= X-Google-Smtp-Source: ABdhPJzoPEcKBhlObnABxMAkn3QVuUczHXUwTPLpPJvdyaaltd8pqj2J58Ved9sC2cuHZe0NJImR+Q== X-Received: by 2002:a0c:be89:0:b0:42c:38b2:9d17 with SMTP id n9-20020a0cbe89000000b0042c38b29d17mr13861381qvi.50.1648305830795; Sat, 26 Mar 2022 07:43:50 -0700 (PDT) Received: from jesse-desktop.jtp-bos.lab (146-115-144-188.s4282.c3-0.nwt-cbr1.sbo-nwt.ma.cable.rcncustomer.com. [146.115.144.188]) by smtp.gmail.com with ESMTPSA id 70-20020a370649000000b0067b4cd8ffbasm4908918qkg.60.2022.03.26.07.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Mar 2022 07:43:49 -0700 (PDT) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com List-Id: Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de, olof@lixom.net, soc@kernel.org, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, sebastian.reichel@collabora.com, cniedermaier@dh-electronics.com, Mr.Bossman075@gmail.com, clin@suse.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v1 11/12] ARM: dts: imx: Add i.MXRT1170-EVK support Date: Sat, 26 Mar 2022 10:43:12 -0400 Message-Id: <20220326144313.673549-12-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220326144313.673549-1-Mr.Bossman075@gmail.com> References: <20220326144313.673549-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 and M4 core. The EVK provides 64 MB SDRAM, 128 MB Quad SPI flash, Micro SD card socket, two USB 2.0 OTG, and two Ethernet ports. This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC Cc: Giulio Benetti Signed-off-by: Jesse Taube --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imxrt1170-evk.dts | 126 +++++++++++++ arch/arm/boot/dts/imxrt1170.dtsi | 278 ++++++++++++++++++++++++++++ 3 files changed, 406 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imxrt1170-evk.dts create mode 100644 arch/arm/boot/dts/imxrt1170.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 07acd6189cae..87ae30818f39 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -724,7 +724,8 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb dtb-$(CONFIG_SOC_IMXRT) += \ - imxrt1050-evk.dtb + imxrt1050-evk.dtb \ + imxrt1170-evk.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/imxrt1170-evk.dts b/arch/arm/boot/dts/imxrt1170-evk.dts new file mode 100644 index 000000000000..fc3b41de8215 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1170-evk.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +/dts-v1/; +#include "imxrt1170.dtsi" +#include "imxrt1170-pinfunc.h" + +/ { + model = "NXP imxrt1170-evk board"; + compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + gpio7 = &gpio8; + gpio8 = &gpio9; + gpio9 = &gpio10; + gpio10 = &gpio11; + gpio11 = &gpio12; + gpio12 = &gpio13; + mmc0 = &usdhc1; + serial0 = &lpuart1; + usbphy0 = &usbphy1; + }; + + memory@20240000 { + device_type = "memory"; + reg = <0x20240000 0xf0000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio9 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1 + IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IOMUXC_GPIO_AD_11_USB_OTG1_OC 0xf1 + >; + }; + + pinctrl_usbotg1_id: pinctrl_usbotg1_id { + fsl,pins = < + IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IOMUXC_GPIO_AD_32_USDHC1_CD_B + 0x1B000 + IOMUXC_GPIO_AD_34_USDHC1_VSELECT + 0xB069 + IOMUXC_GPIO_SD_B1_00_USDHC1_CMD + 0x17061 + IOMUXC_GPIO_SD_B1_01_USDHC1_CLK + 0x17061 + IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 + 0x17061 + IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 + 0x17061 + IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 + 0x17061 + IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 + 0x17061 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + status = "okay"; + broken-cd; +}; diff --git a/arch/arm/boot/dts/imxrt1170.dtsi b/arch/arm/boot/dts/imxrt1170.dtsi new file mode 100644 index 000000000000..fb53347571a9 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1170.dtsi @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + */ + +#include "armv7-m.dtsi" +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + size = <0x40000>; + no-map; + linux,dma-default; + }; + }; + + clocks { + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + rcosc16M: rcosc16M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + osc32k: osc32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + osc3M: osc3M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + }; + + soc { + anatop: anatop@40c84000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x40c84000 0x4000>; + }; + + clks: ccm@40cc0000 { + compatible = "fsl,imxrt1170-ccm"; + reg = <0x40cc0000 0x4000>; + clocks = <&osc>, <&rcosc16M>, <&osc32k>; + clock-names = "osc", "rcosc16M", "osc32k"; + #clock-cells = <1>; + }; + + edma1: dma-controller@40070000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x40070000 0x4000>, + <0x40074000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1170_CLK_BUS>, + <&clks IMXRT1170_CLK_M4>; + }; + + gpio1: gpio@4012c000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x4012c000 0x4000>; + interrupts = <100>, <101>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@40130000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40130000 0x4000>; + interrupts = <102>, <103>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@40134000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40134000 0x4000>; + interrupts = <104>, <105>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@40138000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40138000 0x4000>; + interrupts = <106>, <107>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@4013c000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x4013c000 0x4000>; + interrupts = <108>, <109>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@40140000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40140000 0x4000>; + interrupts = <61>, <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@40c5c000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40c5c000 0x4000>; + interrupts = <99>, <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@40c60000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40c60000 0x4000>; + interrupts = <99>, <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio9: gpio@40c64000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40c64000 0x4000>; + interrupts = <99>, <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio10: gpio@40c68000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40c68000 0x4000>; + interrupts = <99>, <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio11: gpio@40c6c000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40c6c000 0x4000>; + interrupts = <99>, <99>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio12: gpio@40c70000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40c70000 0x4000>; + interrupts = <61>, <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio13: gpio@40ca0000 { + compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio"; + reg = <0x40ca0000 0x4000>; + interrupts = <93>, <93>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt: timer@400ec000 { + compatible = "fsl,imxrt1170-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + reg = <0x400ec000 0x4000>; + interrupts = <119>; + clocks = <&osc3M>; + clock-names = "per"; + }; + + iomuxc: iomuxc@400e8000 { + compatible = "fsl,imxrt1170-iomuxc"; + reg = <0x400e8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + lpuart1: serial@4007c000 { + compatible = "fsl,imxrt1170-lpuart", "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x4007c000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1170_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + usdhc1: mmc@40418000 { + compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x40418000 0x10000>; + interrupts = <133>; + clocks = <&clks IMXRT1170_CLK_BUS>, + <&clks IMXRT1170_CLK_BUS>, + <&clks IMXRT1170_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <4000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + + usbmisc1: usbmisc@40430200 { + compatible = "fsl,imx7ulp-usbmisc"; + #index-cells = <1>; + reg = <0x40430200 0x200>; + }; + + usbotg1: usb@40430000 { + compatible = "fsl,imx7ulp-usb"; + reg = <0x40430000 0x200>; + interrupts = <136>; + clocks = <&clks IMXRT1170_CLK_USB>; + phys = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbphy1: usb-phy@40434000 { + compatible = "fsl,imx7ulp-usbphy"; + reg = <0x40434000 0x1000>; + interrupts = <90>; + clocks = <&clks IMXRT1170_CLK_USB>; + #phy-cells = <0>; + }; + + }; +};