From patchwork Thu Jun 2 22:16:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gore X-Patchwork-Id: 12868209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1FAFC43334 for ; Thu, 2 Jun 2022 22:16:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id A8A68C385A5; Thu, 2 Jun 2022 22:16:56 +0000 (UTC) Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id D04A1C3411C for ; Thu, 2 Jun 2022 22:16:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org D04A1C3411C Authentication-Results: smtp.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.kernel.org; spf=fail smtp.mailfrom=broadcom.com Received: by mail-pj1-f42.google.com with SMTP id l20-20020a17090a409400b001dd2a9d555bso5948269pjg.0 for ; Thu, 02 Jun 2022 15:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=SQ2nKwTsggHkqUB0ACUb1f7+uog6AkJh2TQSgR7UR7I=; b=IQnJllevfjPAX/xVkwfuFdlc3NCkuR+lr/TcHopIBdGi7I/WThZzUSbp6ZEnCOJ2FM TrQvwHZbHKn4mYb2r2KHZMODZbq8es09VIg9ktImXsckmWVkwAm+REvN6b1jfXyc47RR es5zp85w5knXPei1MMW/0vKmWE1neRpSwty9w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=SQ2nKwTsggHkqUB0ACUb1f7+uog6AkJh2TQSgR7UR7I=; b=Ln6PEy8IuhkBfEftx1HtzgYtPdaX4zCiTKX5xgS922DsNx8/Q8PoiJDEDmLwU5O75r OxJ1pAlJJ2UR4TapHt2h7dDmwWHwH6//iT2Ru0RpU4Q3GeOHYxjB3F+j3HeQ4H6dkIum SsP6b/z+2AgySPQdKc5y1edbSR87mSJCMnmMcoBcnO/vJqqCtb9cI4qeaODhU5f7iJHl rOXuEf+RzfPfNARsL5FvPhQSe8hAVfH5ieU+Rw4JUfmrjI08W3pCKv1zQ9N4ba39BO0P hGkven7iipWBu8HxeYXkyJX1opzLNZrZmlWUX+Hjqp7pkv6HkJUmeqd7vTgqAEbrMxVE GXEA== X-Gm-Message-State: AOAM531jlJ3S5hw4P7vLjDW9Ey1RK8oIHLC4LuarGMZQwsZtwOmRCldZ Mgz1+Ay7k0cpfY+EKRcinPnhkA== X-Google-Smtp-Source: ABdhPJx+R2Tcy9vTujgOhufMaVUKvSQKeyfZf+0o5QPEVWoXAnrTgy3Mz7TtbuVobzYC5EdWYyN2+A== X-Received: by 2002:a17:902:f710:b0:15f:165f:b50b with SMTP id h16-20020a170902f71000b0015f165fb50bmr7258003plo.158.1654208214124; Thu, 02 Jun 2022 15:16:54 -0700 (PDT) Received: from linuxpc-ThinkServer-TS140.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id z10-20020a056a001d8a00b00518d0707b52sm3903369pfw.208.2022.06.02.15.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 15:16:52 -0700 (PDT) From: Anand Gore To: Linux ARM List List-Id: Cc: kursad.oney@broadcom.com, florian.fainelli@broadcom.com, tomer.yacoby@broadcom.com, samyon.furman@broadcom.com, dan.beygelman@broadcom.com, William Zhang , joel.peshkin@broadcom.com, Anand Gore , Arnd Bergmann , Broadcom internal kernel review list , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH v4 1/3] ARM: dts: add dts files for bcmbca soc 6878 Date: Thu, 2 Jun 2022 15:16:44 -0700 Message-Id: <20220602151639.v4.1.I0ef47baf3d32d36f823c539c3da3735a6b3e855b@changeid> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220602221646.3127512-1-anand.gore@broadcom.com> References: <20220602221646.3127512-1-anand.gore@broadcom.com> MIME-Version: 1.0 Add dts for ARMv7 based broadband SoC BCM6878. bcm6878.dtsi is the SoC description dts header and bcm96878.dts is a simple dts file for Broadcom BCM96878 Reference board that only enable the UART port. Signed-off-by: Anand Gore --- (no changes since v2) Changes in v2: - Fix psci, GIC dts entries arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/bcm6878.dtsi | 110 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm96878.dts | 30 +++++++++ 3 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm6878.dtsi create mode 100644 arch/arm/boot/dts/bcm96878.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d9ac59524408..553fef458926 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -183,7 +183,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ bcm947622.dtb \ - bcm963178.dtb + bcm963178.dtb \ + bcm96878.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi new file mode 100644 index 000000000000..a7dff596fe1e --- /dev/null +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6878", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = ; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts new file mode 100644 index 000000000000..8fbc175cb452 --- /dev/null +++ b/arch/arm/boot/dts/bcm96878.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6878.dtsi" + +/ { + model = "Broadcom BCM96878 Reference Board"; + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};