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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id i20-20020aa79094000000b0065a1b05193asm4604268pfa.185.2023.06.22.07.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 07:13:53 -0700 (PDT) From: Jacky Huang To: mturquette@baylibre.com, sboyd@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org List-Id: Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, soc@kernel.org, krzysztof.kozlowski+dt@linaro.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH v3 2/3] clk: nuvoton: Update all constant hex values to lowercase Date: Thu, 22 Jun 2023 14:13:42 +0000 Message-Id: <20230622141343.13595-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622141343.13595-1-ychuang570808@gmail.com> References: <20230622141343.13595-1-ychuang570808@gmail.com> MIME-Version: 1.0 From: Jacky Huang The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be lowercase. Signed-off-by: Jacky Huang --- drivers/clk/nuvoton/clk-ma35d1.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 8dfa762494fe..733750dda0f4 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -22,19 +22,19 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define REG_CLK_PWRCTL 0x00 #define REG_CLK_SYSCLK0 0x04 #define REG_CLK_SYSCLK1 0x08 -#define REG_CLK_APBCLK0 0x0C +#define REG_CLK_APBCLK0 0x0c #define REG_CLK_APBCLK1 0x10 #define REG_CLK_APBCLK2 0x14 #define REG_CLK_CLKSEL0 0x18 -#define REG_CLK_CLKSEL1 0x1C +#define REG_CLK_CLKSEL1 0x1c #define REG_CLK_CLKSEL2 0x20 #define REG_CLK_CLKSEL3 0x24 #define REG_CLK_CLKSEL4 0x28 -#define REG_CLK_CLKDIV0 0x2C +#define REG_CLK_CLKDIV0 0x2c #define REG_CLK_CLKDIV1 0x30 #define REG_CLK_CLKDIV2 0x34 #define REG_CLK_CLKDIV3 0x38 -#define REG_CLK_CLKDIV4 0x3C +#define REG_CLK_CLKDIV4 0x3c #define REG_CLK_CLKOCTL 0x40 #define REG_CLK_STATUS 0x50 #define REG_CLK_PLL0CTL0 0x60 @@ -44,18 +44,18 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define REG_CLK_PLL3CTL0 0x90 #define REG_CLK_PLL3CTL1 0x94 #define REG_CLK_PLL3CTL2 0x98 -#define REG_CLK_PLL4CTL0 0xA0 -#define REG_CLK_PLL4CTL1 0xA4 -#define REG_CLK_PLL4CTL2 0xA8 -#define REG_CLK_PLL5CTL0 0xB0 -#define REG_CLK_PLL5CTL1 0xB4 -#define REG_CLK_PLL5CTL2 0xB8 -#define REG_CLK_CLKDCTL 0xC0 -#define REG_CLK_CLKDSTS 0xC4 -#define REG_CLK_CDUPB 0xC8 -#define REG_CLK_CDLOWB 0xCC -#define REG_CLK_CKFLTRCTL 0xD0 -#define REG_CLK_TESTCLK 0xF0 +#define REG_CLK_PLL4CTL0 0xa0 +#define REG_CLK_PLL4CTL1 0xa4 +#define REG_CLK_PLL4CTL2 0xa8 +#define REG_CLK_PLL5CTL0 0xb0 +#define REG_CLK_PLL5CTL1 0xb4 +#define REG_CLK_PLL5CTL2 0xb8 +#define REG_CLK_CLKDCTL 0xc0 +#define REG_CLK_CLKDSTS 0xc4 +#define REG_CLK_CDUPB 0xc8 +#define REG_CLK_CDLOWB 0xcc +#define REG_CLK_CKFLTRCTL 0xd0 +#define REG_CLK_TESTCLK 0xf0 #define REG_CLK_PLLCTL 0x40 #define PLL_MODE_INT 0