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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id i20-20020aa79094000000b0065a1b05193asm4604268pfa.185.2023.06.22.07.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 07:13:55 -0700 (PDT) From: Jacky Huang To: mturquette@baylibre.com, sboyd@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org List-Id: Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, soc@kernel.org, krzysztof.kozlowski+dt@linaro.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH v3 3/3] clk: nuvoton: Use clk_parent_data instead of string for parent clock Date: Thu, 22 Jun 2023 14:13:43 +0000 Message-Id: <20230622141343.13595-4-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622141343.13595-1-ychuang570808@gmail.com> References: <20230622141343.13595-1-ychuang570808@gmail.com> MIME-Version: 1.0 From: Jacky Huang For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments, replace the usage of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for all cases. Signed-off-by: Jacky Huang --- drivers/clk/nuvoton/clk-ma35d1.c | 306 ++++++++++++++++++++++--------- 1 file changed, 219 insertions(+), 87 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 733750dda0f4..f1fe7edd21b5 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -63,167 +63,298 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MODE_SS 2 static const struct clk_parent_data ca35clk_sel_clks[] = { - { .index = 0 }, /* HXT */ - { .index = 1 }, /* CAPLL */ - { .index = 2 } /* DDRPLL */ + { .fw_name = "hxt", }, + { .fw_name = "capll", }, + { .fw_name = "ddrpll", }, }; -static const char *const sysclk0_sel_clks[] = { - "epll_div2", "syspll" +static const struct clk_parent_data sysclk0_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, }; -static const char *const sysclk1_sel_clks[] = { - "hxt", "syspll" +static const struct clk_parent_data sysclk1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "syspll", }, }; -static const char *const axiclk_sel_clks[] = { - "capll_div2", "capll_div4" +static const struct clk_parent_data axiclk_sel_clks[] = { + { .fw_name = "capll_div2", }, + { .fw_name = "capll_div4", }, }; -static const char *const ccap_sel_clks[] = { - "hxt", "vpll", "apll", "syspll" +static const struct clk_parent_data ccap_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "vpll", }, + { .fw_name = "apll", }, + { .fw_name = "syspll", }, }; -static const char *const sdh_sel_clks[] = { - "syspll", "apll", "dummy", "dummy" +static const struct clk_parent_data sdh_sel_clks[] = { + { .fw_name = "syspll", }, + { .fw_name = "apll", }, }; -static const char *const dcu_sel_clks[] = { - "epll_div2", "syspll" +static const struct clk_parent_data dcu_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, }; -static const char *const gfx_sel_clks[] = { - "epll", "syspll" +static const struct clk_parent_data gfx_sel_clks[] = { + { .fw_name = "epll", }, + { .fw_name = "syspll", }, }; -static const char *const dbg_sel_clks[] = { - "hirc", "syspll" +static const struct clk_parent_data dbg_sel_clks[] = { + { .fw_name = "hirc", }, + { .fw_name = "syspll", }, }; -static const char *const timer0_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer0_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer1_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer2_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer2_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer3_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer3_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer4_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer4_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer5_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer5_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer6_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer6_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer7_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer7_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer8_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer8_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer9_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer9_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer10_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer10_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer11_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer11_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const uart_sel_clks[] = { - "hxt", "sysclk1_div2", "dummy", "dummy" +static const struct clk_parent_data uart_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "sysclk1_div2", }, }; -static const char *const wdt0_sel_clks[] = { - "dummy", "lxt", "pclk3_div4096", "lirc" +static const struct clk_parent_data wdt0_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wdt1_sel_clks[] = { - "dummy", "lxt", "pclk3_div4096", "lirc" +static const struct clk_parent_data wdt1_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wdt2_sel_clks[] = { - "dummy", "lxt", "pclk4_div4096", "lirc" +static const struct clk_parent_data wdt2_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wwdt0_sel_clks[] = { - "dummy", "dummy", "pclk3_div4096", "lirc" +static const struct clk_parent_data wwdt0_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wwdt1_sel_clks[] = { - "dummy", "dummy", "pclk3_div4096", "lirc" +static const struct clk_parent_data wwdt1_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wwdt2_sel_clks[] = { - "dummy", "dummy", "pclk4_div4096", "lirc" +static const struct clk_parent_data wwdt2_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const spi0_sel_clks[] = { - "pclk1", "apll", "dummy", "dummy" +static const struct clk_parent_data spi0_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, }; -static const char *const spi1_sel_clks[] = { - "pclk2", "apll", "dummy", "dummy" +static const struct clk_parent_data spi1_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, }; -static const char *const spi2_sel_clks[] = { - "pclk1", "apll", "dummy", "dummy" +static const struct clk_parent_data spi2_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, }; -static const char *const spi3_sel_clks[] = { - "pclk2", "apll", "dummy", "dummy" +static const struct clk_parent_data spi3_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, }; -static const char *const qspi0_sel_clks[] = { - "pclk0", "apll", "dummy", "dummy" +static const struct clk_parent_data qspi0_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, }; -static const char *const qspi1_sel_clks[] = { - "pclk0", "apll", "dummy", "dummy" +static const struct clk_parent_data qspi1_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, }; -static const char *const i2s0_sel_clks[] = { - "apll", "sysclk1_div2", "dummy", "dummy" +static const struct clk_parent_data i2s0_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, }; -static const char *const i2s1_sel_clks[] = { - "apll", "sysclk1_div2", "dummy", "dummy" +static const struct clk_parent_data i2s1_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, }; -static const char *const can_sel_clks[] = { - "apll", "vpll" +static const struct clk_parent_data can_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "vpll", }, }; -static const char *const cko_sel_clks[] = { - "hxt", "lxt", "hirc", "lirc", "capll_div4", "syspll", - "ddrpll", "epll_div2", "apll", "vpll", "dummy", "dummy", - "dummy", "dummy", "dummy", "dummy" +static const struct clk_parent_data cko_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "hirc", }, + { .fw_name = "lirc", }, + { .fw_name = "capll_div4", }, + { .fw_name = "syspll", }, + { .fw_name = "ddrpll", }, + { .fw_name = "epll_div2", }, + { .fw_name = "apll", }, + { .fw_name = "vpll", }, }; -static const char *const smc_sel_clks[] = { - "hxt", "pclk4" +static const struct clk_parent_data smc_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "pclk4", }, }; -static const char *const kpi_sel_clks[] = { - "hxt", "lxt" +static const struct clk_parent_data kpi_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, }; static const struct clk_div_table ip_div_table[] = { @@ -255,11 +386,12 @@ static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char *name static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, - const char *const *parents, int num_parents) + const struct clk_parent_data *pdata, + int num_pdata) { - return devm_clk_hw_register_mux(dev, name, parents, num_parents, - CLK_SET_RATE_NO_REPARENT, reg, shift, - width, 0, &ma35d1_lock); + return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); } static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *name,