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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde1dfaesm13443450f8f.90.2025.02.10.14.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 14:10:05 -0800 (PST) From: Alexander Sverdlin To: soc@lists.linux.dev Cc: Alexander Sverdlin , Jisheng Zhang , Chao Wei , Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 3/7] arm64: dts: sophgo: Add initial SG2000 SoC device tree Date: Mon, 10 Feb 2025 23:09:43 +0100 Message-ID: <20250210220951.1248533-4-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250210220951.1248533-1-alexander.sverdlin@gmail.com> References: <20250210220951.1248533-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). Signed-off-by: Alexander Sverdlin --- Changelog: v2: - relocated "memory" node according to DT coding style; - moved GIC node into "soc"; - referring "soc" by label; arch/arm64/boot/dts/sophgo/sg2000.dtsi | 75 ++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 000000000000..98c8d300347c --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) + +#include +#include +#include + +/ { + compatible = "sophgo,sg2000"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + i-cache-size = <32768>; + d-cache-size = <32768>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x20000>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MiB */ + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + always-on; + clock-frequency = <25000000>; + }; +}; + +&soc { + gic: interrupt-controller@1f01000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f01000 0x1000>, + <0x01f02000 0x2000>; + }; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; +}; + +&clk { + compatible = "sophgo,sg2000-clk"; +};