diff mbox series

[v19,05/11] clk: gate: Add devm_clk_hw_register_gate_parent_data()

Message ID 70efe3b8ba941d897599ba8a61ae31984dbd3ed2.1655360818.git.qinjian@cqplus1.com (mailing list archive)
State Superseded
Headers show
Series Add Sunplus SP7021 SoC Support | expand

Commit Message

Qin Jian June 16, 2022, 6:42 a.m. UTC
Add devm_clk_hw_register_gate_parent_data() - devres-managed version
of clk_hw_register_gate_parent_data()

Signed-off-by: Qin Jian <qinjian@cqplus1.com>
---
 include/linux/clk-provider.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c10dc4c65..179346c5c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -567,6 +567,23 @@  struct clk *clk_register_gate(struct device *dev, const char *name,
 	__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
 			       NULL, (flags), (reg), (bit_idx),		      \
 			       (clk_gate_flags), (lock))
+/**
+ * devm_clk_hw_register_gate_parent_data - register a gate clock with the
+ * clock framework
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_data: parent clk data
+ * @flags: framework-specific flags for this clock
+ * @reg: register address to control gating of this clock
+ * @bit_idx: which bit in the register controls gating of this clock
+ * @clk_gate_flags: gate-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags,  \
+				       reg, bit_idx, clk_gate_flags, lock)    \
+	__devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL,	      \
+			       (parent_data), (flags), (reg), (bit_idx),      \
+			       (clk_gate_flags), (lock))
 void clk_unregister_gate(struct clk *clk);
 void clk_hw_unregister_gate(struct clk_hw *hw);
 int clk_gate_is_enabled(struct clk_hw *hw);