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Wed, 5 Oct 2022 20:23:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT009.mail.protection.outlook.com (10.13.173.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Wed, 5 Oct 2022 20:23:40 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 5 Oct 2022 15:23:39 -0500 From: Mario Limonciello To: , , CC: , Mario Limonciello , Subject: [PATCH 0/4] Enable runtime PM more broadly Date: Wed, 5 Oct 2022 15:23:48 -0500 Message-ID: <20221005202353.1269-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT009:EE_|PH7PR12MB7140:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c2b8ab3-44d7-4a9d-e73a-08daa70f7e2c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2022 20:23:40.8472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c2b8ab3-44d7-4a9d-e73a-08daa70f7e2c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7140 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Currently every time a vendor introduces a new USB4 controller changes need to be made in xhci-pci to add the PCI IDs representing the XHCI controller used for tunneling. Due to low power management needs every single integrated Intel and AMD controller have needed to be added. As we already know which controller is used for tunneling by the device links specified in ACPI tables, this is a very good heuristic. This series uses that as a heuristic, pulls out all the IDs added to xhci-pci and then adds the new IDs for those *not* used for tunneling on AMD's Pink Sardine (those are covered by the kernel today). The original RFC that lead to this series and discussion related to it is available here: Link: https://lore.kernel.org/linux-usb/20221004041225.1462336-1-mario.limonciello@amd.com/T/#t Mario Limonciello (4): USB: ACPI: Look for `usb4-host-interface` property xhci-pci: Move PCI IDs for runtime allow into a table xhci-pci: Remove a number of controllers from the runtime PM allowlist xhci-pci: Allow host runtime PM as default for AMD Pink Sardine drivers/usb/core/usb-acpi.c | 9 +++++ drivers/usb/host/xhci-pci.c | 74 +++++++++++++++++-------------------- 2 files changed, 43 insertions(+), 40 deletions(-)