| Message ID | 20230405125759.4201-1-quic_kriskura@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add multiport support for DWC3 controllers | expand |
On Wed, Apr 05, 2023, Krishna Kurapati wrote: > Currently the DWC3 driver supports only single port controller which > requires at most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS > mode. > > This change primarily refactors the Phy logic in core driver to allow > multiport support with Generic Phy's. > > Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2 > are HS+SS capable and 2 are HS only capable). > > Changes in v6: > Updated comments in code after. > Updated variables names appropriately as per review comments. > Updated commit text in patch-2 and added additional info as per review > comments. > The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected > it in this version. > > Changes in v5: > Added DT support for first port of Teritiary USB controller on SA8540-Ride > Added support for reading port info from XHCI Extended Params registers. > > Changes in RFC v4: > Added DT support for SA8295p. > > Changes in RFC v3: > Incase any PHY init fails, then clear/exit the PHYs that > are already initialized. > > Changes in RFC v2: > Changed dwc3_count_phys to return the number of PHY Phandles in the node. > This will be used now in dwc3_extract_num_phys to increment num_usb2_phy > and num_usb3_phy. > > Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its > structure such that the first half is for HS-PHY and second half is for > SS-PHY. > > In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is > present, pass proper SS_IDX else pass -1. > > Link to v5: https://urldefense.com/v3/__https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/__;!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O7oBPDywQ$ > Link to RFC v4: https://urldefense.com/v3/__https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/__;!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5p58Ga7A$ > Link to RFC v3: https://urldefense.com/v3/__https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/*r__;Iw!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5eLTSOZg$ > Link to RFC v2: https://urldefense.com/v3/__https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/*r__;Iw!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5CAsP83Q$ > > Krishna Kurapati (8): > dt-bindings: usb: Add bindings for multiport properties on DWC3 > controller > usb: dwc3: core: Access XHCI address space temporarily to read port > info > usb: dwc3: core: Skip setting event buffers for host only controllers > usb: dwc3: core: Refactor PHY logic to support Multiport Controller > usb: dwc3: qcom: Add multiport controller support for qcom wrapper > arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 > arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB > ports > arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb > controller > > .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ > drivers/usb/dwc3/core.c | 373 ++++++++++++++---- > drivers/usb/dwc3/core.h | 71 +++- > drivers/usb/dwc3/drd.c | 13 +- > drivers/usb/dwc3/dwc3-qcom.c | 28 +- > 8 files changed, 523 insertions(+), 102 deletions(-) > > -- > 2.40.0 > Please check if your patches and mailing client. Looks like they are corrupted. Thanks, Thinh
On 08/04/2023 03:42, Thinh Nguyen wrote: >> Krishna Kurapati (8): >> dt-bindings: usb: Add bindings for multiport properties on DWC3 >> controller >> usb: dwc3: core: Access XHCI address space temporarily to read port >> info >> usb: dwc3: core: Skip setting event buffers for host only controllers >> usb: dwc3: core: Refactor PHY logic to support Multiport Controller >> usb: dwc3: qcom: Add multiport controller support for qcom wrapper >> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 >> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB >> ports >> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb >> controller >> >> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- >> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ >> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ >> drivers/usb/dwc3/core.c | 373 ++++++++++++++---- >> drivers/usb/dwc3/core.h | 71 +++- >> drivers/usb/dwc3/drd.c | 13 +- >> drivers/usb/dwc3/dwc3-qcom.c | 28 +- >> 8 files changed, 523 insertions(+), 102 deletions(-) >> >> -- >> 2.40.0 >> > > Please check if your patches and mailing client. Looks like they are > corrupted. All patches look from patch-syntax and apply fine. What is exactly corrupted? Best regards, Krzysztof
On Sat, Apr 08, 2023, Krzysztof Kozlowski wrote: > On 08/04/2023 03:42, Thinh Nguyen wrote: > >> Krishna Kurapati (8): > >> dt-bindings: usb: Add bindings for multiport properties on DWC3 > >> controller > >> usb: dwc3: core: Access XHCI address space temporarily to read port > >> info > >> usb: dwc3: core: Skip setting event buffers for host only controllers > >> usb: dwc3: core: Refactor PHY logic to support Multiport Controller > >> usb: dwc3: qcom: Add multiport controller support for qcom wrapper > >> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 > >> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB > >> ports > >> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb > >> controller > >> > >> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- > >> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ > >> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ > >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ > >> drivers/usb/dwc3/core.c | 373 ++++++++++++++---- > >> drivers/usb/dwc3/core.h | 71 +++- > >> drivers/usb/dwc3/drd.c | 13 +- > >> drivers/usb/dwc3/dwc3-qcom.c | 28 +- > >> 8 files changed, 523 insertions(+), 102 deletions(-) > >> > >> -- > >> 2.40.0 > >> > > > > Please check if your patches and mailing client. Looks like they are > > corrupted. > > All patches look from patch-syntax and apply fine. What is exactly > corrupted? > Hm... perhaps it's an encoding issue from my mail client then. I get this from my automated checks: <snip> ERROR: spaces required around that '=' (ctx:WxV) #429: FILE: drivers/usb/dwc3/core.h:1697: + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= ^ ERROR: spaces required around that '=' (ctx:VxV) #429: FILE: drivers/usb/dwc3/core.h:1697: + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= ^ ERROR: spaces required around that '=' (ctx:VxE) #429: FILE: drivers/usb/dwc3/core.h:1697: + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= ^ ERROR: do not use assignment in if condition #429: FILE: drivers/usb/dwc3/core.h:1697: + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= ERROR: spaces required around that '=' (ctx:WxV) #433: FILE: drivers/usb/dwc3/core.h:1700: + next =3D XHCI_EXT_CAPS_NEXT(val); ^ ERROR: spaces required around that '+=' (ctx:WxV) #434: FILE: drivers/usb/dwc3/core.h:1701: + offset +=3D next << 2; </snip> The "=" gets encoded to =3D, which is strange. It never happened before. I need to check my mail client. Sorry for the noise. Thanks, Thinh
On 09/04/2023 01:09, Thinh Nguyen wrote: > On Sat, Apr 08, 2023, Krzysztof Kozlowski wrote: >> On 08/04/2023 03:42, Thinh Nguyen wrote: >>>> Krishna Kurapati (8): >>>> dt-bindings: usb: Add bindings for multiport properties on DWC3 >>>> controller >>>> usb: dwc3: core: Access XHCI address space temporarily to read port >>>> info >>>> usb: dwc3: core: Skip setting event buffers for host only controllers >>>> usb: dwc3: core: Refactor PHY logic to support Multiport Controller >>>> usb: dwc3: qcom: Add multiport controller support for qcom wrapper >>>> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 >>>> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB >>>> ports >>>> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb >>>> controller >>>> >>>> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- >>>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ >>>> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ >>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ >>>> drivers/usb/dwc3/core.c | 373 ++++++++++++++---- >>>> drivers/usb/dwc3/core.h | 71 +++- >>>> drivers/usb/dwc3/drd.c | 13 +- >>>> drivers/usb/dwc3/dwc3-qcom.c | 28 +- >>>> 8 files changed, 523 insertions(+), 102 deletions(-) >>>> >>>> -- >>>> 2.40.0 >>>> >>> >>> Please check if your patches and mailing client. Looks like they are >>> corrupted. >> >> All patches look from patch-syntax and apply fine. What is exactly >> corrupted? >> > > Hm... perhaps it's an encoding issue from my mail client then. I get > this from my automated checks: > > <snip> > > ERROR: spaces required around that '=' (ctx:WxV) > #429: FILE: drivers/usb/dwc3/core.h:1697: > + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= > ^ > > ERROR: spaces required around that '=' (ctx:VxV) > #429: FILE: drivers/usb/dwc3/core.h:1697: > + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= > ^ > > ERROR: spaces required around that '=' (ctx:VxE) > #429: FILE: drivers/usb/dwc3/core.h:1697: > + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= > ^ > > ERROR: do not use assignment in if condition > #429: FILE: drivers/usb/dwc3/core.h:1697: > + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id= > > ERROR: spaces required around that '=' (ctx:WxV) > #433: FILE: drivers/usb/dwc3/core.h:1700: > + next =3D XHCI_EXT_CAPS_NEXT(val); > ^ > > ERROR: spaces required around that '+=' (ctx:WxV) > #434: FILE: drivers/usb/dwc3/core.h:1701: > + offset +=3D next << 2; > > </snip> > > > The "=" gets encoded to =3D, which is strange. It never happened before. > I need to check my mail client. Sorry for the noise. I don't see it, but I did not check each patch thoroughly. I also do not know to which patch do you refer to. It is the easiest to reply inline under the block which is corrupted. If you suspect you email client is the cause, just check on lore. Best regards, Krzysztof
Hi, > Krishna Kurapati (8): > dt-bindings: usb: Add bindings for multiport properties on DWC3 > controller > usb: dwc3: core: Access XHCI address space temporarily to read port > info > usb: dwc3: core: Skip setting event buffers for host only controllers > usb: dwc3: core: Refactor PHY logic to support Multiport Controller > usb: dwc3: qcom: Add multiport controller support for qcom wrapper > arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 > arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB > ports > arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb > controller > > .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ > drivers/usb/dwc3/core.c | 373 ++++++++++++++---- > drivers/usb/dwc3/core.h | 71 +++- > drivers/usb/dwc3/drd.c | 13 +- > drivers/usb/dwc3/dwc3-qcom.c | 28 +- > 8 files changed, 523 insertions(+), 102 deletions(-) I tested this series on the sa8540p-ride, with a USB Ethernet adapter plugged into the board. The device shows up as expected: # lsusb -tv /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/2p, 10000M ID 1d6b:0003 Linux Foundation 3.0 root hub |__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=r8152, 5000M ID 0bda:8153 Realtek Semiconductor Corp. RTL8153 Gigabit Ethernet Adapter /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/4p, 480M ID 1d6b:0002 Linux Foundation 2.0 root hub Tested-by: Adrien Thierry <athierry@redhat.com> # sa8540p-ride
On 4/14/2023 12:24 AM, Adrien Thierry wrote: > Hi, > >> Krishna Kurapati (8): >> dt-bindings: usb: Add bindings for multiport properties on DWC3 >> controller >> usb: dwc3: core: Access XHCI address space temporarily to read port >> info >> usb: dwc3: core: Skip setting event buffers for host only controllers >> usb: dwc3: core: Refactor PHY logic to support Multiport Controller >> usb: dwc3: qcom: Add multiport controller support for qcom wrapper >> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 >> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB >> ports >> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb >> controller >> >> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- >> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ >> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ >> drivers/usb/dwc3/core.c | 373 ++++++++++++++---- >> drivers/usb/dwc3/core.h | 71 +++- >> drivers/usb/dwc3/drd.c | 13 +- >> drivers/usb/dwc3/dwc3-qcom.c | 28 +- >> 8 files changed, 523 insertions(+), 102 deletions(-) > > I tested this series on the sa8540p-ride, with a USB Ethernet adapter > plugged into the board. The device shows up as expected: > > # lsusb -tv > /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/2p, 10000M > ID 1d6b:0003 Linux Foundation 3.0 root hub > |__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=r8152, 5000M > ID 0bda:8153 Realtek Semiconductor Corp. RTL8153 Gigabit Ethernet Adapter > /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/4p, 480M > ID 1d6b:0002 Linux Foundation 2.0 root hub > > Tested-by: Adrien Thierry <athierry@redhat.com> # sa8540p-ride > Hi Adrien, Thanks for testing out the patches. Regards, Krishna,
Currently the DWC3 driver supports only single port controller which requires at most two PHYs ie HS and SS PHYs. There are SoCs that has DWC3 controller with multiple ports that can operate in host mode. Some of the port supports both SS+HS and other port supports only HS mode. This change primarily refactors the Phy logic in core driver to allow multiport support with Generic Phy's. Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2 are HS+SS capable and 2 are HS only capable). Changes in v6: Updated comments in code after. Updated variables names appropriately as per review comments. Updated commit text in patch-2 and added additional info as per review comments. The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected it in this version. Changes in v5: Added DT support for first port of Teritiary USB controller on SA8540-Ride Added support for reading port info from XHCI Extended Params registers. Changes in RFC v4: Added DT support for SA8295p. Changes in RFC v3: Incase any PHY init fails, then clear/exit the PHYs that are already initialized. Changes in RFC v2: Changed dwc3_count_phys to return the number of PHY Phandles in the node. This will be used now in dwc3_extract_num_phys to increment num_usb2_phy and num_usb3_phy. Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its structure such that the first half is for HS-PHY and second half is for SS-PHY. In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is present, pass proper SS_IDX else pass -1. Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/ Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/ Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/#r Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/#r Krishna Kurapati (8): dt-bindings: usb: Add bindings for multiport properties on DWC3 controller usb: dwc3: core: Access XHCI address space temporarily to read port info usb: dwc3: core: Skip setting event buffers for host only controllers usb: dwc3: core: Refactor PHY logic to support Multiport Controller usb: dwc3: qcom: Add multiport controller support for qcom wrapper arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++ arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++ drivers/usb/dwc3/core.c | 373 ++++++++++++++---- drivers/usb/dwc3/core.h | 71 +++- drivers/usb/dwc3/drd.c | 13 +- drivers/usb/dwc3/dwc3-qcom.c | 28 +- 8 files changed, 523 insertions(+), 102 deletions(-)