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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f484dc5sm134189166b.171.2024.08.22.08.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 08:28:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, ulf.hansson@linaro.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 00/16] Add initial USB support for the Renesas RZ/G3S SoC Date: Thu, 22 Aug 2024 18:27:45 +0300 Message-Id: <20240822152801.602318-1-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Hi, Series adds initial USB support for the Renesas RZ/G3S SoC. Series is split as follows: - patch 01/16 - add clock reset and power domain support for USB - patch 02-04/16 - add reset control support for a USB signal that need to be controlled before/after the power to USB area is turned on/off. Philipp, Ulf, Geert, all, I detailed my approach for this in patch 04/16, please have a look and let me know your input. Thank you! - patch 05/16 - moves SoC identification to SYSC driver - patch 06-08/16 - updates USB PHY control driver for USB support - patch 09/16 - update documentation for USBHS - patch 10-12/16 - updates the USB PHY driver for USB support - patch 13-15/16 - updates the device tree with USB support - patch 16/16 - enables the reset control driver Thank you, Claudiu Beznea Claudiu Beznea (16): clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: soc: renesas: renesas,rzg2l-sysc: Add #reset-cells for RZ/G3S dt-bindings: reset: renesas,r9a08g045-sysc: Add reset IDs for RZ/G3S SYSC reset soc: renesas: Add SYSC driver for Renesas RZ/G3S soc: renesas: sysc: Move RZ/G3S SoC detection on SYSC driver dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S SoC reset: rzg2l-usbphy-ctrl: Get reset control array reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S dt-bindings: usb: renesas,usbhs: Document RZ/G3S SoC phy: renesas: rcar-gen3-usb2: Add support to initialize the bus dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC arm64: dts: renesas: Add #reset-cells to system controller node arm64: dts: renesas: r9a08g045: Add USB support arm64: dts: renesas: rzg3s-smarc: Enable USB support arm64: defconfig: Enable RZ/G3S SYSC reset driver .../bindings/phy/renesas,usb2-phy.yaml | 4 +- .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 35 +++- .../soc/renesas/renesas,rzg2l-sysc.yaml | 16 ++ .../bindings/usb/renesas,usbhs.yaml | 2 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 120 +++++++++++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 61 +++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/r9a08g045-cpg.c | 17 ++ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 60 ++++++- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-rzg2l-usbphy-ctrl.c | 3 +- drivers/reset/reset-rzg3s-sysc.c | 140 ++++++++++++++++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/renesas-soc.c | 12 -- drivers/soc/renesas/rzg3s-sysc.c | 158 ++++++++++++++++++ .../reset/renesas,r9a08g045-sysc.h | 10 ++ include/linux/soc/renesas/rzg3s-sysc-reset.h | 24 +++ 18 files changed, 648 insertions(+), 24 deletions(-) create mode 100644 drivers/reset/reset-rzg3s-sysc.c create mode 100644 drivers/soc/renesas/rzg3s-sysc.c create mode 100644 include/dt-bindings/reset/renesas,r9a08g045-sysc.h create mode 100644 include/linux/soc/renesas/rzg3s-sysc-reset.h