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Thu, 17 Oct 2024 11:41:08 GMT Received: from hu-uaggarwa-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 04:41:04 -0700 From: Uttkarsh Aggarwal To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Greg Kroah-Hartman , Felipe Balbi , Thinh Nguyen CC: , , , , , Uttkarsh Aggarwal Subject: [PATCH v2 0/2] Add support to ignore single SE0 glitches Date: Thu, 17 Oct 2024 17:10:53 +0530 Message-ID: <20241017114055.13971-1-quic_uaggarwa@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 69v6MbNwFKRVf2rwcvJLPc5iR7TV7cma X-Proofpoint-ORIG-GUID: 69v6MbNwFKRVf2rwcvJLPc5iR7TV7cma X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 mlxscore=0 clxscore=1011 malwarescore=0 mlxlogscore=893 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170079 Currently in few of Qualcomm chips USB (Low speed) mouse not detected showing following errors: usb 1-1: Device not responding to setup address. usb 1-1: device not accepting address 2, error -71 usb 1-1: new low-speed USB device number 3 using xhci-hcd usb 1-1: Device not responding to setup address. usb 1-1: Device not responding to setup address. usb 1-1: device not accepting address 3, error -71 usb usb1-port1: attempt power cycle Based on the Logic analyzer waveforms, It has been identified that there is skew of about 8nS b/w DP & DM linestate signals (o/p of PHY & i/p to controller) at the UTMI interface, Due to this controller is seeing SE0 glitch condition, this is causing controller to pre-maturely assume that PHY has sent all the data & is initiating next packet much early, though in reality PHY is still busy sending previous packets. Enabling the GUCTL1.FILTER_SE0_FSLS_EOP bit29 allows the controller to ignore single SE0 glitches on the linestate during transmission. Only two or more SE0 signals are recognized as a valid EOP. When this feature is activated, SE0 signals on the linestate are validated over two consecutive UTMI/ULPI clock edges for EOP detection. Device mode (FS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then for device LPM handshake, the controller ignores single SE0 glitch on the linestate during transmit. Only two or more SE0 is considered as a valid EOP on FS port. Host mode (FS/LS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then the controller ignores single SE0 glitch on the linestate during transmit. DT patch will be sent separately. Changes in v2: Included bindings update for the quirk. Updated commit text for core patch. Link to v1: https://lore.kernel.org/all/20240823055642.27638-1-quic_uaggarwa@quicinc.com/ Uttkarsh Aggarwal (2): dt-bindings: usb: snps,dwc3: Add snps,filter-se0-fsls-eop quirk usb: dwc3: core: Add support to ignore single SE0 glitches .../devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ drivers/usb/dwc3/core.c | 13 +++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 3 files changed, 23 insertions(+)