| Message ID | 1568983997-20004-4-git-send-email-cchiluve@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ADD interconnect support for Qualcomm DWC3 driver | expand |
Hi Chandana, On Fri, Sep 20, 2019 at 06:23:17PM +0530, cchiluve wrote: > From: Chandana Kishori Chiluveru <cchiluve@codeaurora.org> > > Populate USB DT nodes with interconnect properties. > > Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index fcb9330..e4885f3 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1837,6 +1837,12 @@ > > resets = <&gcc GCC_USB30_PRIM_BCR>; > > + interconnects = <&rsc_hlos MASTER_USB3_0 > + &rsc_hlos SLAVE_EBI1>, > + <&rsc_hlos MASTER_APPSS_PROC > + &rsc_hlos SLAVE_USB3_0>; > + interconnect-names = "usb-ddr", "apps-usb"; > + > usb_1_dwc3: dwc3@a600000 { > compatible = "snps,dwc3"; > reg = <0 0x0a600000 0 0xcd00>; > @@ -1881,6 +1887,12 @@ > > resets = <&gcc GCC_USB30_SEC_BCR>; > > + interconnects = <&rsc_hlos MASTER_USB3_1 > + &rsc_hlos SLAVE_EBI1>, > + <&rsc_hlos MASTER_APPSS_PROC > + &rsc_hlos SLAVE_USB3_1>; > + interconnect-names = "usb-ddr", "apps-usb"; > + > usb_2_dwc3: dwc3@a800000 { > compatible = "snps,dwc3"; > reg = <0 0x0a800000 0 0xcd00>; The patch "arm64: dts: sdm845: Redefine interconnect provider DT nodes" (https://patchwork.kernel.org/patch/11326603/) reorganizes the SDM845 interconnect nodes and the node 'rsc_hlos' ceases to exist.
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fcb9330..e4885f3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1837,6 +1837,12 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&rsc_hlos MASTER_USB3_0 + &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC + &rsc_hlos SLAVE_USB3_0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -1881,6 +1887,12 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&rsc_hlos MASTER_USB3_1 + &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_APPSS_PROC + &rsc_hlos SLAVE_USB3_1>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: dwc3@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>;