From patchwork Wed Dec 18 09:16:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11300029 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 551261892 for ; Wed, 18 Dec 2019 09:17:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 33A3A227BF for ; Wed, 18 Dec 2019 09:17:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="TIli0aFW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727020AbfLRJRi (ORCPT ); Wed, 18 Dec 2019 04:17:38 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:19174 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725799AbfLRJRh (ORCPT ); Wed, 18 Dec 2019 04:17:37 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 18 Dec 2019 01:17:26 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 18 Dec 2019 01:17:36 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 18 Dec 2019 01:17:36 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Dec 2019 09:17:35 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Dec 2019 09:17:35 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 18 Dec 2019 09:17:35 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.64.167]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 18 Dec 2019 01:17:34 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , "Nagarjuna Kristam" Subject: [Patch V2 11/18] usb: gadget: tegra-xudc: use phy_set_mode to set/unset device mode Date: Wed, 18 Dec 2019 14:46:24 +0530 Message-ID: <1576660591-10383-12-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576660591-10383-1-git-send-email-nkristam@nvidia.com> References: <1576660591-10383-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576660646; bh=Mok6MEzH4AJX2i8iqVFyy/vLOjTHdOvbIMksYeCyLkM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=TIli0aFWKN8tvWEPqtySfgSZkTBoHyIcRLMCootEHVV+cgbk8vvPIj9jpwZSLrXz3 qCs/7LLNBoRswh/9NzPB64vn5yeSpz+Bwehx48kwCF3ABFeNnhF8Adw9sTHJ4TzTQQ FPu30BPUy8DBii1Fme1bBNSeyua6hD4R+jzx2fFJ52N27DC9/xMPnqrI+V/8LGkoI8 ueINK96vRDUHT17f+yUJfpn7aV/lt34EjnYhW41iYco264C3OKVWyUnkALhrVLyHg8 veRydVFR9PlWFm2s5izQZSwyubnMVSbCrXGyFbqitQXAiqn9VVKU3T9OXuGqz2JwAu EiDM9OiVBfJBg== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org When device mode is set/uset, vbus override activity is done via exported functions from padctl driver. Use phy_set_mode instead. Signed-off-by: Nagarjuna Kristam --- V2: - No changes in this version --- drivers/usb/gadget/udc/tegra-xudc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 0f27d57..283c320 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -615,7 +615,7 @@ static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc) dev_dbg(xudc->dev, "device mode on\n"); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, true); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_DEVICE); xudc->device_mode = true; @@ -636,7 +636,7 @@ static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc) reinit_completion(&xudc->disconnect_complete); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, false); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT; @@ -716,9 +716,11 @@ static void tegra_xudc_plc_reset_work(struct work_struct *work) if (pls == PORTSC_PLS_INACTIVE) { dev_info(xudc->dev, "PLS = Inactive. Toggle VBUS\n"); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, - false); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, true); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, + USB_ROLE_NONE); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, + USB_ROLE_DEVICE); + xudc->wait_csc = false; } }