From patchwork Mon Jul 27 07:14:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 11686391 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD8E26C1 for ; Mon, 27 Jul 2020 07:16:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B45AB207FC for ; Mon, 27 Jul 2020 07:16:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="V7YgE5Ne" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727057AbgG0HQo (ORCPT ); Mon, 27 Jul 2020 03:16:44 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52175 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727033AbgG0HQo (ORCPT ); Mon, 27 Jul 2020 03:16:44 -0400 X-UUID: 80b9a423517e4aa9a639366fe86a34df-20200727 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=x6c9apllsraX6rv/6S+rjbkHnvqPnQsJAwjR+kPcEbE=; b=V7YgE5NepMNABOjRneQAGmqaJSLYTMzm9BCgDDnyMqx9bR2AD/ji6+nD1PaHqdgIz81g6YamgS897siqayAtWJ6j3sA3D7iKRrYchh0d9E5IXBDWXcBQ+gg9/ZH4bLt0OPOHzndTJE1NG8Ksupou6c9tQyqPYgisckqau+6sLuM=; X-UUID: 80b9a423517e4aa9a639366fe86a34df-20200727 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2117605699; Mon, 27 Jul 2020 15:16:38 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 27 Jul 2020 15:16:35 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 27 Jul 2020 15:16:35 +0800 From: Chunfeng Yun To: Felipe Balbi , Greg Kroah-Hartman CC: Matthias Brugger , Chunfeng Yun , , , , , Eddie Hung Subject: [PATCH 04/11] usb: mtu3: clear interrupts status when disable interrupts Date: Mon, 27 Jul 2020 15:14:53 +0800 Message-ID: <1595834101-13094-4-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1595834101-13094-1-git-send-email-chunfeng.yun@mediatek.com> References: <1595834101-13094-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A8C7A88285639417D4FD77E1C46961D26AEA72226E43EB7A31F8065F0DED3D7E2000:8 X-MTK: N Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org When disable interrupts, will also want to clear their status, ensure it by calling mtu3_intr_status_clear() in mtu3_intr_disable(). Signed-off-by: Chunfeng Yun --- drivers/usb/mtu3/mtu3_core.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c index f3ad1cc..ece5b3e 100644 --- a/drivers/usb/mtu3/mtu3_core.c +++ b/drivers/usb/mtu3/mtu3_core.c @@ -147,17 +147,6 @@ static void mtu3_device_reset(struct mtu3 *mtu) mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); } -/* disable all interrupts */ -static void mtu3_intr_disable(struct mtu3 *mtu) -{ - void __iomem *mbase = mtu->mac_base; - - /* Disable level 1 interrupts */ - mtu3_writel(mbase, U3D_LV1IECR, ~0x0); - /* Disable endpoint interrupts */ - mtu3_writel(mbase, U3D_EPIECR, ~0x0); -} - static void mtu3_intr_status_clear(struct mtu3 *mtu) { void __iomem *mbase = mtu->mac_base; @@ -170,6 +159,18 @@ static void mtu3_intr_status_clear(struct mtu3 *mtu) mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0); /* Clear speed change interrupt status */ mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0); + /* Clear QMU interrupt status */ + mtu3_writel(mbase, U3D_QISAR0, ~0x0); +} + +/* disable all interrupts */ +static void mtu3_intr_disable(struct mtu3 *mtu) +{ + /* Disable level 1 interrupts */ + mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0); + /* Disable endpoint interrupts */ + mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0); + mtu3_intr_status_clear(mtu); } /* enable system global interrupt */ @@ -312,7 +313,6 @@ void mtu3_stop(struct mtu3 *mtu) dev_dbg(mtu->dev, "%s\n", __func__); mtu3_intr_disable(mtu); - mtu3_intr_status_clear(mtu); if (mtu->softconnect) mtu3_dev_on_off(mtu, 0); @@ -600,7 +600,6 @@ static void mtu3_regs_init(struct mtu3 *mtu) /* be sure interrupts are disabled before registration of ISR */ mtu3_intr_disable(mtu); - mtu3_intr_status_clear(mtu); mtu3_csr_init(mtu);