From patchwork Fri Sep 25 06:20:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11799125 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F219B6CA for ; Fri, 25 Sep 2020 06:23:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D736A23447 for ; Fri, 25 Sep 2020 06:23:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="U/WZJy69" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727278AbgIYGXj (ORCPT ); Fri, 25 Sep 2020 02:23:39 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:41569 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727222AbgIYGXd (ORCPT ); Fri, 25 Sep 2020 02:23:33 -0400 X-UUID: b6732976654c4e14a3b22fa8751a5857-20200925 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=M9B+st9EHiLWNz6oa11lg4+mh5nozfsj2SPClhQffMk=; b=U/WZJy69PwYKBURICYjpRd9MArwkhQ587MLSk3YV8FjJcU7BuH4yXaDS3aLp+qilKYZUzJ7YDz7NxgjrDo6GGCIr+aKWsnFBUmnyP4AcMkDTNkU8HTNORegZn7DYJVu7tE+yY+GwRH9fUzSAR3nubJx10HoyhLNPbsT2QPFR/K8=; X-UUID: b6732976654c4e14a3b22fa8751a5857-20200925 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1428776088; Fri, 25 Sep 2020 14:23:26 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 14:23:24 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 14:23:24 +0800 From: Chunfeng Yun To: Felipe Balbi CC: Greg Kroah-Hartman , Matthias Brugger , Florian Fainelli , Chunfeng Yun , Al Cooper , Sasi Kumar , Nathan Chancellor , Colin Ian King , , , , Subject: [PATCH V3 RESEND 07/11] usb: gadget: bdc: avoid precedence issues Date: Fri, 25 Sep 2020 14:20:28 +0800 Message-ID: <1601014832-29726-7-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1601014832-29726-1-git-send-email-chunfeng.yun@mediatek.com> References: <1601014832-29726-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: DBA42CFD313BE9F3C341867BCE3F1BEB4D06B6C3B352AA49DEBF0F0E6201FE382000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add () around macro argument to avoid precedence issues Cc: Florian Fainelli Signed-off-by: Chunfeng Yun Acked-by: Florian Fainelli --- v3: add acked-by Florian v2: add Cc Florian --- drivers/usb/gadget/udc/bdc/bdc.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/usb/gadget/udc/bdc/bdc.h b/drivers/usb/gadget/udc/bdc/bdc.h index 658abef..f8d5958 100644 --- a/drivers/usb/gadget/udc/bdc/bdc.h +++ b/drivers/usb/gadget/udc/bdc/bdc.h @@ -86,20 +86,20 @@ #define BDC_EPSTS5 0x74 #define BDC_EPSTS6 0x78 #define BDC_EPSTS7 0x7c -#define BDC_SRRBAL(n) (0x200 + (n * 0x10)) -#define BDC_SRRBAH(n) (0x204 + (n * 0x10)) -#define BDC_SRRINT(n) (0x208 + (n * 0x10)) -#define BDC_INTCTLS(n) (0x20c + (n * 0x10)) +#define BDC_SRRBAL(n) (0x200 + ((n) * 0x10)) +#define BDC_SRRBAH(n) (0x204 + ((n) * 0x10)) +#define BDC_SRRINT(n) (0x208 + ((n) * 0x10)) +#define BDC_INTCTLS(n) (0x20c + ((n) * 0x10)) /* Extended capability regs */ #define BDC_FSCNOC 0xcd4 #define BDC_FSCNIC 0xce4 -#define NUM_NCS(p) (p >> 28) +#define NUM_NCS(p) ((p) >> 28) /* Register bit fields and Masks */ /* BDC Configuration 0 */ #define BDC_PGS(p) (((p) & (0x7 << 8)) >> 8) -#define BDC_SPB(p) (p & 0x7) +#define BDC_SPB(p) ((p) & 0x7) /* BDC Capability1 */ #define BDC_P64 (1 << 0) @@ -113,7 +113,7 @@ #define BDC_CMD_DVC 0x1 #define BDC_CMD_CWS (0x1 << 5) #define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6) -#define BDC_CMD_EPN(p) ((p & 0x1f) << 10) +#define BDC_CMD_EPN(p) (((p) & 0x1f) << 10) #define BDC_SUB_CMD_ADD (0x1 << 17) #define BDC_SUB_CMD_FWK (0x4 << 17) /* Reset sequence number */ @@ -163,7 +163,7 @@ #define BDC_SPEED_HS 0x3 #define BDC_SPEED_SS 0x4 -#define BDC_PST(p) (p & 0xf) +#define BDC_PST(p) ((p) & 0xf) #define BDC_PST_MASK 0xf /* USPPMS */ @@ -228,7 +228,7 @@ /* status report defines */ #define SR_XSF 0 #define SR_USPC 4 -#define SR_BD_LEN(p) (p & 0xffffff) +#define SR_BD_LEN(p) ((p) & 0xffffff) #define XSF_SUCC 0x1 #define XSF_SHORT 0x3