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Tue, 3 Aug 2021 12:35:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT012.mail.protection.outlook.com (10.13.177.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Tue, 3 Aug 2021 12:35:16 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 3 Aug 2021 07:35:13 -0500 From: Sanjay R Mehta To: , , , CC: , , Sanjay R Mehta Subject: [PATCH v2 1/4] thunderbolt: Intel controller uses BIT(2) for intr auto Date: Tue, 3 Aug 2021 07:34:53 -0500 Message-ID: <1627994096-99972-2-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4c67d835-b40c-4f94-4891-08d9567b259b X-MS-TrafficTypeDiagnostic: BN6PR12MB1490: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2021 12:35:16.1105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c67d835-b40c-4f94-4891-08d9567b259b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1490 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta REG_DMA_MISC_INT_AUTO_CLEAR which is bit 2 in that register is actually Intel specific. As per the USB4 spec bit 17 is used for interrupt auto clear and by default its enabled. Hence limit usage of REG_DMA_MISC_INT_AUTO_CLEAR for Intel controllers and moved this to quirk. Fixes: 046bee1f9ab8 ("thunderbolt: Add MSI-X support") Suggested-by: Mika Westerberg Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 8 ++------ drivers/thunderbolt/quirks.c | 14 ++++++++++++++ drivers/thunderbolt/tb.h | 1 + 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index fa44332..ef01aa6 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -57,8 +57,8 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) u32 old, new; if (ring->irq > 0) { - u32 step, shift, ivr, misc; void __iomem *ivr_base; + u32 step, shift, ivr; int index; if (ring->is_tx) @@ -70,11 +70,7 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) * Ask the hardware to clear interrupt status bits automatically * since we already know which interrupt was triggered. */ - misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); - if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { - misc |= REG_DMA_MISC_INT_AUTO_CLEAR; - iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); - } + quirk_enable_intr_auto_clr(ring); ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; diff --git a/drivers/thunderbolt/quirks.c b/drivers/thunderbolt/quirks.c index b5f2ec7..af6dab9 100644 --- a/drivers/thunderbolt/quirks.c +++ b/drivers/thunderbolt/quirks.c @@ -6,6 +6,7 @@ */ #include "tb.h" +#include "nhi_regs.h" static void quirk_force_power_link(struct tb_switch *sw) { @@ -64,3 +65,16 @@ void tb_check_quirks(struct tb_switch *sw) q->hook(sw); } } + +void quirk_enable_intr_auto_clr(struct tb_ring *ring) +{ + u32 misc; + + if (ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) { + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); + if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { + misc |= REG_DMA_MISC_INT_AUTO_CLEAR; + iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); + } + } +} diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index 725104c..0b8f9d3 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -1122,6 +1122,7 @@ int usb4_port_device_resume(struct usb4_port *usb4); #define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0) void tb_check_quirks(struct tb_switch *sw); +void quirk_enable_intr_auto_clr(struct tb_ring *ring); #ifdef CONFIG_ACPI void tb_acpi_add_links(struct tb_nhi *nhi);