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Tue, 3 Aug 2021 12:35:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT008.mail.protection.outlook.com (10.13.177.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4373.18 via Frontend Transport; Tue, 3 Aug 2021 12:35:20 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 3 Aug 2021 07:35:17 -0500 From: Sanjay R Mehta To: , , , CC: , , Sanjay R Mehta Subject: [PATCH v2 2/4] thunderbolt: Handle ring interrupt by reading intr status Date: Tue, 3 Aug 2021 07:34:54 -0500 Message-ID: <1627994096-99972-3-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> References: <1627994096-99972-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7915cea-10f2-41e5-165e-08d9567b2813 X-MS-TrafficTypeDiagnostic: DM6PR12MB2891: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2021 12:35:20.2501 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7915cea-10f2-41e5-165e-08d9567b2813 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2891 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta As per USB4 spec by default "Disable ISR Auto-Clear" bit is set to 0, and the Tx/Rx ring interrupt status is needs to be cleared. Hence handling it by reading the "Interrupt status" register in the ISR. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index ef01aa6..7ad2202 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -373,11 +373,25 @@ void tb_ring_poll_complete(struct tb_ring *ring) } EXPORT_SYMBOL_GPL(tb_ring_poll_complete); +static void check_and_clear_intr_status(struct tb_ring *ring) +{ + if (!(ring->nhi->pdev->vendor == PCI_VENDOR_ID_INTEL)) { + if (ring->is_tx) + ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE); + else + ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE + + 4 * (ring->nhi->hop_count / 32)); + } +} + static irqreturn_t ring_msix(int irq, void *data) { struct tb_ring *ring = data; spin_lock(&ring->nhi->lock); + check_and_clear_intr_status(ring); spin_lock(&ring->lock); __ring_interrupt(ring); spin_unlock(&ring->lock);