| Message ID | 1635751025-25906-1-git-send-email-zhuyinbo@loongson.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] usb: xhci: add LPM quirk for ensuring uPD720201 into D3 state after S5 | expand |
Hi On 1.11.2021 9.17, Yinbo Zhu wrote: > After S5, any pci device should into D3 state that if supported, but the > uPD720201 was not and it may be the cause of xhci firmware and cause > OSPM power consumption is more higher that S5 than S4. I think xhci HCD > can add a quirk ensure it into D3 state after S5 that is appropriate > and this patch was to add LPM quirk and set PCI_D3hot to uPD720201 pmsc > register in xhci_pci_shutdown to fix xhci power consumption issue. > > Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> I think we need a better understanding of the underlying issue before adding a quirk like this. Is this a known issue with the uPD720201 controller firmware? or is it an issue with ACPI table entries not supporting the proper D state in BIOS on the tested platform, or something completely different? Also, LPM usually refers to "Link Power Management" in the xHCI spec. This is about the U1 and U2 link states for the connected USB device. If we end up needing a new xhci quirk it will need a new name. Thanks -Mathias
在 2021/11/1 下午5:18, Mathias Nyman 写道: > Hi > > On 1.11.2021 9.17, Yinbo Zhu wrote: >> After S5, any pci device should into D3 state that if supported, but the >> uPD720201 was not and it may be the cause of xhci firmware and cause >> OSPM power consumption is more higher that S5 than S4. I think xhci HCD >> can add a quirk ensure it into D3 state after S5 that is appropriate >> and this patch was to add LPM quirk and set PCI_D3hot to uPD720201 pmsc >> register in xhci_pci_shutdown to fix xhci power consumption issue. >> >> Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> > I think we need a better understanding of the underlying issue before > adding a quirk like this. > > Is this a known issue with the uPD720201 controller firmware? or is it > an issue with ACPI table entries not supporting the proper D state in BIOS > on the tested platform, or something completely different? Yes, and I notice other xhci hc doesn't encounter this power consumption issue I think that xhci firmware may be set D3 after s5, but the xhci firmware code isn't visible, in addition I find that test platform the _PS3 method wasn't implemented in acpi table which can make device into S3, Bios team didn't add it for some platform reason and I think xhci hcd to ensure device into D3 state after s5 that is appropriate > > Also, LPM usually refers to "Link Power Management" in the xHCI spec. > This is about the U1 and U2 link states for the connected USB device. > > If we end up needing a new xhci quirk it will need a new name. > > Thanks > -Mathias Hi Mathias, I had changed the quirk that replace XHCI_LPM_QUIRK with XHCI_LWP_QUIRK as v2 version patch. please view the v2 version patch. Thanks, Yinbo.
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 2c9f25c..f97bb64 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -265,6 +265,7 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) pdev->device == 0x0014) { xhci->quirks |= XHCI_TRUST_TX_LENGTH; xhci->quirks |= XHCI_ZERO_64B_REGS; + xhci->quirks |= XHCI_LPM_QUIRK; } if (pdev->vendor == PCI_VENDOR_ID_RENESAS && pdev->device == 0x0015) { @@ -608,7 +609,8 @@ static void xhci_pci_shutdown(struct usb_hcd *hcd) xhci_shutdown(hcd); /* Yet another workaround for spurious wakeups at shutdown with HSW */ - if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) + if (xhci->quirks & XHCI_SPURIOUS_WAKEUP || + xhci->quirks & XHCI_LPM_QUIRK) pci_set_power_state(pdev, PCI_D3hot); } #endif /* CONFIG_PM */ diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index dca6181..5f790202 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1899,6 +1899,7 @@ struct xhci_hcd { #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) #define XHCI_NO_SOFT_RETRY BIT_ULL(40) #define XHCI_BROKEN_D3COLD BIT_ULL(41) +#define XHCI_LPM_QUIRK BIT_ULL(42) unsigned int num_active_eps; unsigned int limit_active_eps;
After S5, any pci device should into D3 state that if supported, but the uPD720201 was not and it may be the cause of xhci firmware and cause OSPM power consumption is more higher that S5 than S4. I think xhci HCD can add a quirk ensure it into D3 state after S5 that is appropriate and this patch was to add LPM quirk and set PCI_D3hot to uPD720201 pmsc register in xhci_pci_shutdown to fix xhci power consumption issue. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> --- drivers/usb/host/xhci-pci.c | 4 +++- drivers/usb/host/xhci.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-)