| Message ID | 1644207958-18287-1-git-send-email-quic_ugoswami@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 117b4e96c7f362eb6459543883fc07f77662472c |
| Headers | show |
| Series | usb: dwc3: gadget: Prevent core from processing stale TRBs | expand |
On Mon, Feb 07, 2022 at 09:55:58AM +0530, Udipto Goswami wrote: > With CPU re-ordering on write instructions, there might > be a chance that the HWO is set before the TRB is updated > with the new mapped buffer address. > And in the case where core is processing a list of TRBs > it is possible that it fetched the TRBs when the HWO is set > but before the buffer address is updated. > Prevent this by adding a memory barrier before the HWO > is updated to ensure that the core always process the > updated TRBs. > > Fixes: f6bafc6a1c9 ("usb: dwc3: convert TRBs into bitshifts") > Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com> > --- > v1: For an ep the trbs can be reused, and if cpu re-ordering also > takes place, there is a change that the HWO will get set even before > the trb bpl/bph are updated which will lead controller to access a > stale buffer address from the previous transactions. > > drivers/usb/dwc3/gadget.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c > index 520031b..183b909 100644 > --- a/drivers/usb/dwc3/gadget.c > +++ b/drivers/usb/dwc3/gadget.c > @@ -1291,6 +1291,19 @@ static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, > if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) > trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); > > + /* > + * As per data book 4.2.3.2TRB Control Bit Rules section > + * > + * The controller autonomously checks the HWO field of a TRB to determine if the > + * entire TRB is valid. Therefore, software must ensure that the rest of the TRB > + * is valid before setting the HWO field to '1'. In most systems, this means that > + * software must update the fourth DWORD of a TRB last. > + * > + * However there is a possibility of CPU re-ordering here which can cause > + * controller to observe the HWO bit set prematurely. > + * Add a write memory barrier to prevent CPU re-ordering. > + */ > + wmb(); > trb->ctrl |= DWC3_TRB_CTRL_HWO; > Looks good to me. FWIW, Reviewed-by: Pavankumar Kondeti <quic_pkondeti@quicinc.com> It is very similar to what we have in xHC during TRB preparation. commit 576667bad341516edc4e18eb85acb0a2b4c9c9d9 Author: Mathias Nyman <mathias.nyman@linux.intel.com> Date: Fri Jan 15 18:19:06 2021 +0200 xhci: make sure TRB is fully written before giving it to the controller Thanks, Pavan
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 520031b..183b909 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1291,6 +1291,19 @@ static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); + /* + * As per data book 4.2.3.2TRB Control Bit Rules section + * + * The controller autonomously checks the HWO field of a TRB to determine if the + * entire TRB is valid. Therefore, software must ensure that the rest of the TRB + * is valid before setting the HWO field to '1'. In most systems, this means that + * software must update the fourth DWORD of a TRB last. + * + * However there is a possibility of CPU re-ordering here which can cause + * controller to observe the HWO bit set prematurely. + * Add a write memory barrier to prevent CPU re-ordering. + */ + wmb(); trb->ctrl |= DWC3_TRB_CTRL_HWO; dwc3_ep_inc_enq(dep);
With CPU re-ordering on write instructions, there might be a chance that the HWO is set before the TRB is updated with the new mapped buffer address. And in the case where core is processing a list of TRBs it is possible that it fetched the TRBs when the HWO is set but before the buffer address is updated. Prevent this by adding a memory barrier before the HWO is updated to ensure that the core always process the updated TRBs. Fixes: f6bafc6a1c9 ("usb: dwc3: convert TRBs into bitshifts") Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com> --- v1: For an ep the trbs can be reused, and if cpu re-ordering also takes place, there is a change that the HWO will get set even before the trb bpl/bph are updated which will lead controller to access a stale buffer address from the previous transactions. drivers/usb/dwc3/gadget.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)