| Message ID | 20190509201142.10543-4-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | usb: Add host and device support for RZ/A2 | expand |
On Thu, 2019-05-09 at 15:11 -0500, Chris Brandt wrote: > The RZ/A2 has an optional dedicated 48MHz clock input for the PLL. > If a clock node named 'usb_x1' exists and set to non-zero, then we can > assume we want it use it. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > --- > v2: > * use 'usb_x1' clock node instead of 'renesas,uses_usb_x1' property > --- > drivers/phy/renesas/phy-rcar-gen3-usb2.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c > index 1322185a00a2..1ebb08f8323f 100644 > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c > @@ -34,6 +34,7 @@ > #define USB2_VBCTRL 0x60c > #define USB2_LINECTRL1 0x610 > #define USB2_ADPCTRL 0x630 > +#define USB2_PHYCLK_CTRL 0x644 > > /* INT_ENABLE */ > #define USB2_INT_ENABLE_UCOM_INTEN BIT(3) > @@ -110,6 +111,7 @@ struct rcar_gen3_chan { > bool extcon_host; > bool is_otg_channel; > bool uses_otg_pins; > + bool uses_usb_x1; > }; > > /* > @@ -391,6 +393,9 @@ static int rcar_gen3_phy_usb2_init(struct phy *p) > void __iomem *usb2_base = channel->base; > u32 val; > > + if (channel->uses_usb_x1) > + writel(0x00000001, usb2_base + USB2_PHYCLK_CTRL); ^^^^ avoid magic number? > + > /* Initialize USB2 part */ > val = readl(usb2_base + USB2_INT_ENABLE); > val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits; > @@ -582,10 +587,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct rcar_gen3_chan *channel; > + struct device_node *usb_x1_clk; > struct phy_provider *provider; > struct resource *res; > const struct phy_ops *phy_usb2_ops; > int irq, ret = 0, i; > + u32 freq_usb = 0; > > if (!dev->of_node) { > dev_err(dev, "This driver needs device tree\n"); > @@ -630,6 +637,13 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) > } > } > > + usb_x1_clk = of_find_node_by_name(NULL, "usb_x1"); > + if (usb_x1_clk) { > + of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb); > + if (freq_usb) > + channel->uses_usb_x1 = true; > + } > + > /* > * devm_phy_create() will call pm_runtime_enable(&phy->dev); > * And then, phy-core will manage runtime pm for this device.
Hi Chrisさん Thank you for the patch! > From: Chris Brandt, Sent: Friday, May 10, 2019 5:12 AM > > The RZ/A2 has an optional dedicated 48MHz clock input for the PLL. > If a clock node named 'usb_x1' exists and set to non-zero, then we can > assume we want it use it. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > --- > v2: > * use 'usb_x1' clock node instead of 'renesas,uses_usb_x1' property > --- > drivers/phy/renesas/phy-rcar-gen3-usb2.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) <snip> > @@ -582,10 +587,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > struct rcar_gen3_chan *channel; > + struct device_node *usb_x1_clk; > struct phy_provider *provider; > struct resource *res; > const struct phy_ops *phy_usb2_ops; > int irq, ret = 0, i; > + u32 freq_usb = 0; > > if (!dev->of_node) { > dev_err(dev, "This driver needs device tree\n"); > @@ -630,6 +637,13 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) > } > } > > + usb_x1_clk = of_find_node_by_name(NULL, "usb_x1"); > + if (usb_x1_clk) { > + of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb); > + if (freq_usb) > + channel->uses_usb_x1 = true; > + } > + We need to call of_node_put(usb_x1_clk); here. By the way, we can also use devm_clk_get() for it like the following driver: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/renesas/rcar-usb2-clock-sel.c#n135 Best regards, Yoshihiro Shimoda > /* > * devm_phy_create() will call pm_runtime_enable(&phy->dev); > * And then, phy-core will manage runtime pm for this device. > -- > 2.16.1
Hi Simoda-san, Chris, On Fri, May 10, 2019 at 6:17 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > > From: Chris Brandt, Sent: Friday, May 10, 2019 5:12 AM > > > > The RZ/A2 has an optional dedicated 48MHz clock input for the PLL. > > If a clock node named 'usb_x1' exists and set to non-zero, then we can > > assume we want it use it. > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > --- > > v2: > > * use 'usb_x1' clock node instead of 'renesas,uses_usb_x1' property > > --- > > drivers/phy/renesas/phy-rcar-gen3-usb2.c | 14 ++++++++++++++ > > @@ -630,6 +637,13 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) > > } > > } > > > > + usb_x1_clk = of_find_node_by_name(NULL, "usb_x1"); > > + if (usb_x1_clk) { > > + of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb); > > + if (freq_usb) > > + channel->uses_usb_x1 = true; > > + } > > + > > We need to call of_node_put(usb_x1_clk); here. > > By the way, we can also use devm_clk_get() for it like the following driver: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/renesas/rcar-usb2-clock-sel.c#n135 +1 devm_clk_get() and clk_get_rate() is the way to go. Gr{oetje,eeting}s, Geert
On Thu, May 09, 2019, Chunfeng Yun wrote: > > + if (channel->uses_usb_x1) > > + writel(0x00000001, usb2_base + USB2_PHYCLK_CTRL); > ^^^^ avoid magic number? OK. Chris
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 1322185a00a2..1ebb08f8323f 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -34,6 +34,7 @@ #define USB2_VBCTRL 0x60c #define USB2_LINECTRL1 0x610 #define USB2_ADPCTRL 0x630 +#define USB2_PHYCLK_CTRL 0x644 /* INT_ENABLE */ #define USB2_INT_ENABLE_UCOM_INTEN BIT(3) @@ -110,6 +111,7 @@ struct rcar_gen3_chan { bool extcon_host; bool is_otg_channel; bool uses_otg_pins; + bool uses_usb_x1; }; /* @@ -391,6 +393,9 @@ static int rcar_gen3_phy_usb2_init(struct phy *p) void __iomem *usb2_base = channel->base; u32 val; + if (channel->uses_usb_x1) + writel(0x00000001, usb2_base + USB2_PHYCLK_CTRL); + /* Initialize USB2 part */ val = readl(usb2_base + USB2_INT_ENABLE); val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits; @@ -582,10 +587,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct rcar_gen3_chan *channel; + struct device_node *usb_x1_clk; struct phy_provider *provider; struct resource *res; const struct phy_ops *phy_usb2_ops; int irq, ret = 0, i; + u32 freq_usb = 0; if (!dev->of_node) { dev_err(dev, "This driver needs device tree\n"); @@ -630,6 +637,13 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) } } + usb_x1_clk = of_find_node_by_name(NULL, "usb_x1"); + if (usb_x1_clk) { + of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb); + if (freq_usb) + channel->uses_usb_x1 = true; + } + /* * devm_phy_create() will call pm_runtime_enable(&phy->dev); * And then, phy-core will manage runtime pm for this device.
The RZ/A2 has an optional dedicated 48MHz clock input for the PLL. If a clock node named 'usb_x1' exists and set to non-zero, then we can assume we want it use it. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- v2: * use 'usb_x1' clock node instead of 'renesas,uses_usb_x1' property --- drivers/phy/renesas/phy-rcar-gen3-usb2.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)