From patchwork Thu May 9 20:11:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 10937671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FAE8112C for ; Thu, 9 May 2019 20:36:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 825CF28707 for ; Thu, 9 May 2019 20:36:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7673A289BC; Thu, 9 May 2019 20:36:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3069D28707 for ; Thu, 9 May 2019 20:36:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727091AbfEIUgp (ORCPT ); Thu, 9 May 2019 16:36:45 -0400 Received: from pbmsgap01.intersil.com ([192.157.179.201]:34932 "EHLO pbmsgap01.intersil.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726939AbfEIUgk (ORCPT ); Thu, 9 May 2019 16:36:40 -0400 Received: from pps.filterd (pbmsgap01.intersil.com [127.0.0.1]) by pbmsgap01.intersil.com (8.16.0.27/8.16.0.27) with SMTP id x49KCZiT018120; Thu, 9 May 2019 16:12:56 -0400 Received: from pbmxdp02.intersil.corp (pbmxdp02.pb.intersil.com [132.158.200.223]) by pbmsgap01.intersil.com with ESMTP id 2scabqgu0v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 09 May 2019 16:12:56 -0400 Received: from pbmxdp03.intersil.corp (132.158.200.224) by pbmxdp02.intersil.corp (132.158.200.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.1531.3; Thu, 9 May 2019 16:12:54 -0400 Received: from localhost.localdomain (132.158.202.108) by pbmxdp03.intersil.corp (132.158.200.224) with Microsoft SMTP Server id 15.1.1531.3 via Frontend Transport; Thu, 9 May 2019 16:12:54 -0400 From: Chris Brandt To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Simon Horman , Yoshihiro Shimoda CC: Geert Uytterhoeven , Sergei Shtylyov , , , , "Chris Brandt" Subject: [PATCH v2 04/15] dt-bindings: rcar-gen3-phy-usb2: Document use of usb_x1 Date: Thu, 9 May 2019 15:11:31 -0500 Message-ID: <20190509201142.10543-5-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20190509201142.10543-1-chris.brandt@renesas.com> References: <20190509201142.10543-1-chris.brandt@renesas.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-05-09_02:,, signatures=0 X-Proofpoint-Spam-Details: rule=junk_notspam policy=junk score=0 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=833 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905090115 X-Proofpoint-Spam-Reason: mlx Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the optional renesas,uses_usb_x1 property. Signed-off-by: Chris Brandt --- v2: * removed 'use_usb_x1' option * document that 'usb_x1' clock node will be detected to determine if 48MHz clock exists --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index d46188f450bf..79d8360d92e5 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -28,7 +28,9 @@ Required properties: followed by the generic version. - reg: offset and length of the partial USB 2.0 Host register block. -- clocks: clock phandle and specifier pair(s). +- clocks: clock phandle and specifier pair(s). For SoCs that have a separate + dedicated 48MHz USB_X1 input, if a 'usb_x1' clock node exists and is + set to non-zero, the PHY will use the 48MHZ input for the PLL. - #phy-cells: see phy-bindings.txt in the same directory, must be <1> (and using <0> is deprecated).